A sub-sense amplifier includes a semiconductor substrate, a first pair of complementary transistors, a second pair of complementary transistors, and at least one ground transistor. The first pair and second pair of complementary transistors and the ground transistor are formed on the semiconductor substrate. The first pair of complementary transistors are disposed in line symmetry with a center line of the sub-sense amplifier as a symmetry axis, and gates of the first pair of complementary transistors are coupled to a node. The second pair of complementary transistors are also disposed in line symmetry with the center line, wherein the current directions of the second pair of complementary transistors are the same. Sources and drains of the first pair of complementary transistors are coupled to gates and sources of the second pair of complementary transistors, respectively. The ground transistor connects in series with the second pair of complementary transistors.

A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.

A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.

A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

A semiconductor memory module for shared memory access implements memory-centric structures using a quasi-volatile memory. In one embodiment, the memory module for shared memory access includes a memory cube providing high capacity memory coupled to multiple multi-port memories to support simultaneous memory access at multiple memory interfaces. In other embodiments, a memory module incorporates a processor to implement computational memory architecture. In some embodiments, a mini core memory system implements a memory architecture for providing direct and parallel memory access to a mini processor core array.

Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.

A page buffer circuit includes a plurality of page buffers connected to a plurality of bitlines. Each of the plurality of page buffers includes a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node. Each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node.

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.

Storage devices include a memory array comprised of a plurality of memory devices. As memory array density increases, multi-pass programming is utilized to reduce negative effects to neighboring memory devices. The use of multi-pass programming requires longer access to the data being programmed. To avoid adding additional lower density or controller memory, data within a host memory is accessed multiple times as needed to provide pieces of data to the memory array, which is configured to comply with the utilized multi-pass programming method. The expected order of the multi-pass programming method can be determined to generate one or more memory pipeline instruction processing queues to direct the components of the storage device memory pipeline to access, re-access, and process the host data in a specific order necessary for delivery to the memory array to comply with the utilized multi-pass programming method.