A memory system includes at least one memory die and a controller coupled to the at least one memory die via a data path. The at least one memory die includes plural memory planes and a register storing operation statuses and operation results regarding the respective memory planes. The controller transfers a first status check command to the at least one memory die and receives a first response including the operation statuses and the operation results regarding the respective memory planes.

Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

A memory module has a registering clock driver (RCD) that issues two column address strobe (CAS) commands with a single memory access command to exchange a double amount of data per dynamic random access memory (DRAM) device per memory access command. With double the amount of data per DRAM device, the memory module can provide double the pseudo channels as compared to a memory module where a single CAS command is issued per access command. The RCD can time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the command/address (CA) bus.

The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.

An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to control access to the NAND memory as two or more groups of memory cells, provide independent operations for the two or more groups of memory cells, share a voltage regulator among at least two of the two or more groups of memory cells, and provide a target constant voltage from the shared voltage regulator to a target group of the two or more groups of memory cells in an independent operation for the target group. Other examples are disclosed and claimed.

Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

A method of operating a memory comprising a plurality of memory planes is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of the plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicating a busy or a ready state of the corresponding memory plane, and (ii) a corresponding plane array ready (PARDY) signal indicating a busy or a ready state of the corresponding memory array of the corresponding memory plane, such that a plurality of PRDY signals and a plurality of PARDY signals are generated corresponding to the plurality of memory planes. Execution of a memory command for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PARDY signals.