A semiconductor device includes a monitoring circuit suitable for generating a monitoring signal indicating whether a speed of a memory clock signal is changed based on a speed information signal representing speed information of the memory clock signal; a cycle control circuit suitable for generating a refresh cycle control signal for controlling a refresh cycle based on a system clock signal, the memory clock signal, the monitoring signal and a refresh flag signal; and a control circuit suitable for generating the memory clock signal and the refresh flag signal based on the speed information signal, the system clock signal and the refresh cycle control signal.

A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

According to an embodiment, a semiconductor device includes a control circuit. The control circuit is configured to receive a first command and execute, based on the first command, a first operation and a second operation. The second operation is executed after the first operation. The control circuit is further configured to output a first signal from a start of the first operation to a start of the second operation. The first signal indicates that the semiconductor device is in a busy state in which the semiconductor device refrains from accepting, from an external controller, a second command for execution of the first operation and a third command for execution of the second operation.

A memory circuit includes a pre-charging circuit and a control circuit. The pre-charging circuit includes a first pre-charging unit, a second pre-charging unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal; the first pre-charging unit is connected with the first power supply terminal, the first control terminal and the data terminal; the second pre-charging unit is connected with the second power supply terminal, the second control terminal and the data terminal. The control circuit is configured to in response to a memory being in a row active state and not performing a reading-writing operation, control, through the second pre-charging unit, the data terminal and the second power supply terminal to be disconnected, and control, through the first pre-charging unit, the data terminal and the first power supply terminal to be disconnected.

A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.

A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

A ternary content addressable memory (TCAM) device comprising an input interface having a first input for receiving first data and a second input for receiving second data; and a memory configured to write the first data into an address selected row of the memory at the same time that a comparison is performed between the second data and at least one other row of the memory different from the address selected row. More particularly, the input interface may further have a third input for receiving a search enable signal and a fourth input for receiving a write enable signal, wherein the memory is configured to write the first data and perform the comparison in response to assertion of the search enable signal at the same time as assertion of the write enable signal. An associated method is also provided.

A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.

A memory device includes a pair of memory cells, an analog-to-digital converter (ADC), and a processing circuit. The pair of memory cells has a first memory cell and a second memory cell. The ADC, having a first input terminal and a second input terminal, is configured to convert a first data signal at the first input terminal and a second data signal at the second input terminal into a digital output indicating a data value associated with a particular state stored in the pair of memory cells. The processing circuit, coupled to a storage node of the first memory cell, a storage node of the second memory cell, and the first and the second input terminals, is configured to selectively adjust the first data signal and the second data signal according to first data stored in the first memory cell and second data stored in the second memory cell.