A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.

A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.

The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.

Provided herein may be a storage device configured to check a status of a memory device based on data read without output of a status check command, and determine a subsequent command to be generated. The storage device may include a memory device and a memory controller configured to control the memory device. The memory device may include a read data generator configured to generate new read data including both read data corresponding to a read command received from the memory controller and information indicating a status of the memory device. The memory controller may include: a status information determiner configured to determine the status of the memory device based on the new read data received from the read data generator and generate status information and a command generator configured to generate a command to be output to the memory device based on the status information.

A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

A multilevel content addressable memory, a multilevel coding method and a multilevel searching method are provided. The multilevel coding method includes the following steps. A highest decimal value of a multilevel-bit binary data is obtained. A length of a digital string data is set as being the highest decimal value of the multilevel-bit binary data. The multilevel-bit binary data is converted into the digital string data. If a content of the multilevel-bit binary data is an exact value, a number of an indicating bit in the digital string data is the exact value.

A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.

A pseudo-analog memory computing circuit includes at least one input circuit, at least one output circuit and at least one pseudo-analog memory computing unit. Each pseudo-analog memory computing unit is coupled between one of the at least one input circuit and one of the at least one output circuit and has at least one weight mode. Each pseudo-analog memory computing unit generates at least first computing result for a coupled output circuit according to a weight of a selected weight mode and at least one input signals of a coupled input circuit.

A memory system includes a nonvolatile memory, and a memory controller configured to control the nonvolatile memory. The nonvolatile memory stores a busy table. The memory controller loads the busy table and controls a chip enable signal for the nonvolatile memory based on the busy table.

A circuit for signal transmission, memory, and method for signal transmission are provided. The circuit includes: a signal processing circuit, configured to receive an input first signal, obtain a second signal by processing the first signal in a preset processing manner, and take the second signal as an output signal of the signal processing circuit; and a selection circuit, configured to receive the input first signal, the second signal and a control signal, and take the first signal or the second signal as an output signal of the selection circuit according to the control signal.