Technology to provide a multi-phase clocking scheme for a memory device includes generating, based on a first clock signal having a first frequency, multi-phase clock signals for a memory device having a second frequency, where the second frequency is a fraction of the first frequency, generating local clock signals for data channels of the memory device based on the multi-phase clock signals, where the local clock signals are synchronous with respective rising edges of the multi-phase clock signals, and providing output data for the data channels of the memory device in an output data sequence based on the local clock signals. In some embodiments, the second frequency is one-half of the first frequency, and the multi-phase clock signals are four-phase clock signals. In some embodiments, the output data is clocked out at an effective rate equal to the first frequency based on the local clock signals.

A memory device and a glitch prevention method thereof are provided. The memory device includes a data strobe signal input circuitry, a transfer signal generating circuitry, a data alignment circuitry, and a blocking circuitry. The data strobe signal input circuitry is configured to input a data strobe signal. The transfer signal generating circuitry is configured to generate a transfer signal with pulses in synchronization with rising edges or falling edges of the data strobe signal in response to a transfer command. The data alignment circuitry is configured to align a data signal to be transferred in response to the generated transfer signal. The blocking circuitry is configured to block an input of the data strobe signal over a postamble timing of the data strobe signal according to a number of bursts counted in each time of data transfer.

A pipe latch circuit includes a data latch circuit configured to latch an input data based on an input control signal and output the latched input data as a latch data based on an output control signal, a sense amplification circuit configured to sense and amplify the latch data based on a sum output control signal, and a data driving circuit configured to drive an output data from the latch data based on the sum output control signal.

A data synthesizer includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to latch a first data under control of a first latch clock signal. The second input circuit is configured to latch a second data under control of the first latch clock signal. A phase of the first data is the same as a phase of the second data. The output circuit is connected to the first input circuit and the second input circuit. The output circuit is configured to output the first data and the second data in sequence.

A semiconductor chip capable of improving signal quality includes a host device, a first memory device which is spaced part from the host device and connected to the host device, a repeater module which is connected to the host device and the first memory device, and a second memory device which is spaced apart from the host device and connected to the repeater module. The first memory device receives a data signal from the host device and generates a recovery clock signal, using the data signal. The repeater module receives the recovery clock signal from the first memory device, receives a first input signal from the host device, and samples the first input signal on the basis of the recovery clock signal to generate a sampling signal. The second memory device receives the sampling signal.

A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

An electronic device includes a dock dividing circuit configured to generate sampling clocks, alignment clocks and output clocks by dividing a frequency of a write clock; and a data alignment circuit configured to, in a first operation mode, receive input data having any one level among a first level to a fourth level and generate alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks, and to, in a second operation mode, receive the input data having any one level of the first level and the fourth level and generate the alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks.

A semiconductor integrated circuit has a reception circuit configured to receive a strobe signal of which a logic is intermittently switched in synchronization with a data signal, an output circuit configured to extract a low frequency component including at least a DC component of the strobe signal received by the reception circuit and to output a first signal, and a comparison circuit configured to compare a signal level of the first signal with a threshold level. The reception circuit is configured to change a boost amount of a high frequency component different from the low frequency component of the strobe signal based on a comparison result obtained by the comparison circuit.

A memory device according to the present invention may comprise: a memory cell array in which memory cells are connected in matrix form to word lines and bit lines; a plurality of mergers connected in series to transfer data that is read from a selected memory cell among the memory cells included in the memory cell array and is transformed into one of a direct current form or a pulse form; and a sorter that synchronizes an edge of first output data, output by one of the plurality of mergers, with an edge of a control pulse, thereby delaying the edge of the first output data. First data, which is either data bit “0” or data bit “1”, can be input to the mergers in the form of a direct current of first logic, and second data, which is another piece of data, can be input to the mergers in the form of a pulse that changes from the first logic to the second logic and back to the first logic. When the first data is input, the sorter can allow the first data to pass as-is and output the first data as second output data in the form of a direct current of the first logic. When a first edge that changes from the second logic to the first logic is input, the sorter can delay the first edge by synchronizing the same with a rising edge or falling edge of the control pulse, and output the first edge as the second output data.