According to one embodiment, a semiconductor memory device includes a memory including a memory cell array, and an input/output pin configured to transfer data, a command, and an address from an external to the memory. The memory includes a termination circuit provided between the input/output pin and the memory cell array, and configured to supply a first voltage having a first amplitude in a first transfer mode and supply a second voltage having a second amplitude in a second transfer mode, a first intermediate value of the first amplitude being different from a second intermediate value of the second amplitude.

The present invention relates to a storage device (300, 400) and to a method of controlling a storage device (300, 400). A storage device (300, 400) according to the invention comprises a plurality of information storage units (101, 201, 302), each comprising an optically transmissive memory element (104, 306), an optically transmissive light-receiving device (102, 304), and an optically transmissive control unit (103, 305) connected to the memory element (104, 306) and the light-receiving device (102, 304). The components are optically transmissive such that a request for information data stored on the optically transmissive memory element (104, 306) may be received from any direction. Thereby, an optical signal (316, 309, 422) comprising a request for information may be received by several light-receiving devices (102, 304) simultaneously enabling a fast retrieval of information data stored on a storage device (300, 400) comprising several information storage units (101, 201, 302).

The disclosure provides for high bandwidth processing through the sharing of memory dies over a plurality of computing dies via an optical interchange. The optical interchange may be configured so as to operate as both an optical switch and optical demultiplexer. The optical switch configuration for the optical interchange allows for data to be written from any computing die to one of a plurality of memory dies via an optical connection. The optical demultiplexer configuration allows for data to be broadcast from a memory die to a plurality of the computing dies.

Multi-chip electro-photonic networks for interconnecting multiple circuit packages via photonic channels. Examples of a computing system include a first circuit package, a second circuit package, and one or more inter-chip bidirectional photonic channels interconnecting the first and second circuit packages. The first circuit package can include one or more memory nodes. The second circuit package can include multiple compute nodes and intra-chip bidirectional photonic channels interconnecting the compute nodes.

Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.

An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

Multi-chip electro-photonic networks for interconnecting multiple circuit packages via photonic channels. Examples of a computing system include a first circuit package, a second circuit package, and one or more inter-chip bidirectional photonic channels interconnecting the first and second circuit packages. The first circuit package can include one or more memory nodes. The second circuit package can include multiple compute nodes and intra-chip bidirectional photonic channels interconnecting the compute nodes.