A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.

A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

A semiconductor device may implement a command-over-data function on a multi-level signaling data bus architectures. The multi-level signaling data bus architecture may support a multi-level communication architecture that includes a plurality of channels each including conversion of M bitstreams to N multi-level signals, where M is greater than N. A bitstream includes a plurality of bits provided serially, with each bit of the bitstream provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus, and to transmit commands using at least a second assigned state of the data bus.

A signal sampling circuit includes the following: a signal input circuit, configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal; a first instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to a first clock signal to obtain a first chip select clock signal; a second instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a second chip select clock signal; and an instruction decoding circuit, configured to perform decoding and sampling processing on the to-be-processed instruction signal according to be to-be-processed chip select signal and one of the first chip select clock signal and the second chip select clock signal to obtain a target instruction signal.

A computing system architecture is presented for decoupling execution of workload by crossbar arrays and similar memory modules. The computing system includes: a data bus; a core controller connected to the data bus; and a plurality of local tiles connected to the data bus. Each local tile in the plurality of local tiles includes a local controller and at least one memory module, where the memory module performs computation using the data stored in memory without reading the data out of the memory.

A memory device includes a pair of memory cells, an analog-to-digital converter (ADC), and a processing circuit. The pair of memory cells has a first memory cell and a second memory cell. The ADC, having a first input terminal and a second input terminal, is configured to convert a first data signal at the first input terminal and a second data signal at the second input terminal into a digital output indicating a data value associated with a particular state stored in the pair of memory cells. The processing circuit, coupled to a storage node of the first memory cell, a storage node of the second memory cell, and the first and the second input terminals, is configured to selectively adjust the first data signal and the second data signal according to first data stored in the first memory cell and second data stored in the second memory cell.

Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.

A memory controller for accessing a memory, comprises a holding circuit which holds a plurality of read or write access requests from a bus master, a read/write control circuit which selects one of the access requests in the holding circuit and issues a read command or a write command; and an active control circuit which selects the access request held in the holding circuit and issues an active command, wherein the active control circuit includes a generation circuit that generates number of activated read commands and number of activated write commands, and a selection circuit that, when the number of activated read commands is not less a threshold, issues the active command of an read access, and when the number of activated write commands is not less than the threshold, issues the active command of a write access.