The present disclosure discloses a memory access interface device. A clock generation circuit generates a reference clock signal. A fake data strobe signal generation circuit receives the reference clock signal and delays a read enable signal from a memory access controller to enable an output of the reference clock signal to generate a fake data strobe signal. A real data strobe signal generation circuit receives a data strobe signal from a memory device and delays the read enable signal to enable an output of the data strobe signal to generate a real data strobe signal. A data reading circuit samples a data signal from the memory device according to a sampling signal to generate a read data signal to the memory access controller. A selection circuit selects the fake and the real data strobe signals as the sampling signal respectively under a single and a double data rate modes.

Provided are an operating method of a host device, an operating method of a memory device, and a memory system. The operating method of a host device includes transmitting a request command for performing an eye-opening monitor (EOM) operation to a memory device, transmitting a parameter for performing the EOM operation to the memory device, transmitting pattern data for performing the EOM operation to the memory device, and receiving a first response signal including a result of the EOM operation performed based on the parameter and the pattern data from the memory device.

A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

The present technology relates to an electronic device. According to the present technology, a memory controller may include a training controller, a training data storage, and a machine learning processor. The training controller may perform training of correcting interface signals exchanged with a memory device, generate training data that is a result of the training, and output the training data as sample training data based on a comparison result of a training reference and the training data. The training data storage may store training history information including plural pieces of sample training data. The machine learning processor may update the training reference through machine learning based on the training history information.

An electronic system includes a controller configured to detect a bank in a standby state for a write operation between a first bank and a second bank during a refresh operation period and output data for performing a post-write operation to the bank in the standby state for the write operation. The electronic system also includes an electronic device including the first and second banks. The electronic device is configured to latch the data in an input/output control circuit connected to the bank in the standby state for the write operation.