Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

A spin orbit torque-based spintronics device that includes a ferromagnet layer having a first surface and a second surface opposed to each other, a metal layer and a spacer layer covering the first surface and the second surface of the ferromagnet layer, respectively, and an dielectric layer covering either the metal layer or the spacer layer. Also disclosed are two related spin orbit torque-based spintronics devices and methods of using these three spintronics devices.

Memory cells and methods of forming thereof are disclosed. The memory cell includes a substrate and first and second select transistors. The first select transistor serves as a write selector and the second select transistor serves as a read selector. The gate of first select transistor is coupled to a write wordline (WL_w) and the gate of the second select transistor is coupled to a read/write wordline (WL_r/w). The source regions of the first and second select transistors are coupled to a source line (SL). A body well is disposed in the substrate. The body well serves as a body of the first and second select transistors. A back bias is applied to the body of the select transistors. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled with a bitline (BL) and the first and the second select transistors.

A magnetic device that includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque and an in-plane magnetized free layer having a magnetization vector having at least a first stable state and a second stable state. The magnetic device also includes a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque can combine. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. An application of a voltage pulse, having either positive or negative polarity and a selected amplitude and duration, through the magnetic device causes the magnetization vector to oscillate between the first stable state and the second stable state for a portion of the duration regardless of an initial state of the magnetization vector.

A gesture manipulation method and a gaming system are disclosed herein. The gesture manipulation method is suitable for an electronic apparatus including a touch sensor and means for displaying. The gesture manipulation method includes following steps. A gesture input is detected by the touch sensor when a visual card image is displayed on the means for displaying and the visual card image shows a back side of at least a playing card. When at least one contact point of the gesture input is detected to move along a specific pattern relative to the visual card image, a corresponding function is triggered or the visual card image is adjusted in response to the gesture input moved along the specific pattern.

In one embodiment, a desirable (e.g., substantially 100%) SOT switching probability is achieved in a SOT device by applying in-plane input current as one or more pulses having a tuned pulse width. In the case of a single pulse, pulse width may be selected as a single tuned pulse width or a range of pulse widths that avoid a specific pulse width determined to cause a switch-back response. In the case of multiple pulses, pulse width, a time interval between pulses and other factors such as intensities may be selected to prevent a switch-back response. Further, SOT switching speed may be achieved by reducing incubation delay through modification of an external magnetic field or input current density applied to the SOT device.

Provided is a spin current magnetization rotational element, including: a first ferromagnetic metal layer for a magnetization direction to be changed; and a spin-orbit torque wiring which extends in a second direction intersecting a first direction that is a plane-orthogonal direction of the first ferromagnetic metal layer, the first ferromagnetic metal layer being located on one surface of the spin-orbit torque wiring, wherein the spin-orbit torque wiring has a structure in which a spin conduction layer and an interfacial spin generation layer are alternately laminated in the first direction, a number of a plurality of the interfacial spin generation layers is two or more, and at least one of the plurality of the interfacial spin generation layer is made of a compound.

According to one embodiment, a magnetic storage device includes memory cells, wherein each of the memory cell includes: a wiring including a first ferromagnetic layer and a first nonmagnetic layer disposed on the first ferromagnetic layer; a magnetoresistive effect element including a second ferromagnetic layer disposed on the first nonmagnetic layer, a third ferromagnetic layer, and a second nonmagnetic layer disposed between the second and the third ferromagnetic layer; a first transistor having a first terminal connected to the first ferromagnetic layer, and a second terminal connected to a source line; and a second transistor having a first terminal connected to the third ferromagnetic layer, and a second terminal connected to a bit line.

According to one embodiment, a magnetic storage device includes a first and a second magnetoresistive effect element, which are disposed in an arrangement pattern including a plurality of arrangement areas, and in each of which a second ferromagnetic layer and a third ferromagnetic layer are antiferromagnetically coupled. A magnetization orientation of the third ferromagnetic layer of the first magnetoresistive effect element is antiparallel to a magnetization orientation of the third ferromagnetic layer of the second magnetoresistive effect element. The first magnetoresistive effect element is disposed in an arrangement area randomly positioned with respect to an arrangement area in which the second magnetoresistive effect element is disposed.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.