An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve the density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semi-conductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

In one embodiment, a spin torque device uses a thick (e.g., >1 nm, and preferably >=2-6 nm) ferrimagnet (FIM) layer, instead of a thin (e.g., <1-2 nm) FM layer in the device's stack. The FIM layer may be composed of a cobalt-gadolinium (CoGd) alloy, cobalt-terbium (CoTb) multilayers, or other materials that provide anti-ferromagnetic coupling between two sub-lattices. Negative exchange interaction between the two sub-lattices of the FIM may allow for low current switching. High thermal stability and external magnetic field resistance may also be achieved.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

An initialization process is disclosed for a perpendicular magnetic tunnel junction (p-MTJ) wherein the switching error rate is reduced from a typical range of 30-100 ppm to less than 10 ppm. In one embodiment, an in-plane magnetic field is applied after a final anneal step is performed during memory device fabrication such that all magnetizations in the free layer, and AP1 and AP2 pinned layers are temporarily aligned in-plane. After the applied field is removed, interfacial perpendicular magnetic anisotropy (PMA) at a tunnel barrier/AP1 interface induces a single AP1 magnetic domain with a magnetization in a first vertical direction. Interfacial PMA at a FL/tunnel barrier interface affords a single FL domain with magnetization in the first direction or opposite thereto. AP2 magnetization is opposite to the first direction as a result of antiferromagnetic coupling with the AP1 layer. Alternatively, a perpendicular-to-plane magnetic field may be applied for initialization.

According to one embodiment, a magnetic device includes a magnetoresistive effect element including a first ferromagnet, a conductor, and an oxide provided between the first ferromagnet and the conductor, the oxide including a first oxide of a rare-earth element and a second oxide of an element of which a covalent radius is smaller than a covalent radius of the rare-earth element.

A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfO.sub.x), tantalum oxide (TaO.sub.x), or titanium dioxide (TiO.sub.x), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.

The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device a magnetic memory component and a current selector component coupled to the magnetic memory component. The current selector component includes a first transistor having a first gate with a corresponding first threshold voltage. The first transistor comprises a charge storage layer configured to selectively store charge so as to adjust a current through the first transistor. The memory device further includes control circuitry configured to determine a bit error rate of the magnetic memory component and adjust a charge stored in the charge storage layer based on the determined bit error rate.

According to one embodiment, a magnetic device includes: a first electrode above a substrate, the first electrode including a first portion and a second portion adjacent to the first portion in a direction parallel to a surface of the substrate; a second electrode above the first electrode; a first magnetic layer between the first electrode and the second electrode; a second magnetic layer between the first magnetic layer and the second electrode; and a non-magnetic layer between the first magnetic layer and the second magnetic layer, wherein an upper face of the first portion is located closer to the substrate than an upper face of the second portion.

In the method for stabilizing a spin element according to an aspect of the disclosure, the spin element includes a current-carrying part extending in a first direction, and an element part laminated on one surface of the current-carrying part and including a ferromagnetic material, a current pulse having a predetermined current value or higher is applied at a predetermined temperature in the first direction of the current-carrying part such that a total pulse application time is equal to or longer than a predetermined time.