Systems and methods for confirming the presence of a person or asset for a given purpose, and recording this information in a distributed ledger. The distributed ledger records and confirms presence indicia in connection with a transaction said facilitates remote and/or automated signatures. The systems and methods detect the presence of one or more humans and/or computing devices at a specific location at the time of a transaction, and contemporaneously recording information concerning the transaction in a distributed ledger. Presence can be determined using network presence sensing (NPS), other types of sensors, or the combination of NPS with other sensors.

A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

Provided is an electronic device including a first electrode; a second electrode facing the first electrode; and an active layer between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes a first surface that is closest to the active layer and a second surface that is farthest from the active layer, a size of a cross-sectional horizontal area at the first surface is smaller than a size of a cross-sectional horizontal area at the second surface, the active layer includes a first region, which vertically overlaps the first surface, and a second region outside the first region, and a thickness of the active layer in the first region is smaller than a thickness of the active layer in the second region.

Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.

The present disclosure relates to a memory device based on a ferroelectric capacitor, which includes a control unit for writing data into a memory cell or reading data from the memory cell and a plurality of memory cells arranged in an array; each memory cell includes an external interface, a first switch, a transistor, a first capacitor and a second capacitor, wherein at least one of the first capacitor and the second capacitor is a ferroelectric capacitor; the first switch has a first port connected with a first word line, a second port connected with a bit line, and a third port connected with one end of the first capacitor; and the transistor has a gate electrode connected with another end of the first capacitor and one end of the second capacitor, a source electrode connected with a first read terminal, and a drain electrode connected with a second read terminal, wherein another end of the second capacitor is connected with a second word line. According to the present disclosure, a polarized state of the ferroelectric capacitor in the memory cell is held or changed based on hysteresis characteristics of the ferroelectric capacitor, and the control unit is used to write data into or read data from the memory cell, which can implement non-destructive reading of data and longer endurance of a write operation.

Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.