Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.

The present disclosure provides a memory circuit, a memory device and an operating method of the memory device. The memory device includes a storage transistor, a variable capacitance device and a control transistor. The variable capacitance device is electrically connected to the gate of the storage transistor, and the control transistor is connected to the storage transistor in series.

Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.

A memory circuit includes a memory array and a control circuit. A first column of the memory array includes a select line, first and second bit lines, a first subset of memory cells coupled to the select line and the first bit line, and a second subset of memory cells coupled to the select line and the second bit line. The control circuit is configured to simultaneously activate each of the select line and the first bit line and, during a period in which the select line and first bit line are simultaneously activated, activate a first plurality of word lines, each word line of the first plurality of word lines being coupled to a memory cell of the first subset of memory cells.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes depositing a grid layer over a substrate. The grid layer is patterned to form a grid structure. The grid structure comprises a plurality of sidewalls defining a plurality of openings. A ferroelectric layer is deposited over the substrate. The ferroelectric layer fills the plurality of openings and is disposed along the plurality of sidewalls of the grid structure. An upper conductive structure is formed over the grid structure.

Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.