Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

[Object] To provide a semiconductor element capable of realizing an element having a nonvolatile memory capable of stably storing highly integrated data, a nonvolatile memory device, a multiply-accumulate operation device, and a method of manufacturing the semiconductor element. [Solving means] A semiconductor element according to an embodiment of the present technology includes a plurality of cell blocks. The plurality of cell blocks are configured by connecting a plurality of cell portions in series with each other, the plurality of cell portions each having a MOSFET for controlling conduction of a channel portion and a resistor connected in parallel to the channel portion, and configured to store data by a resistance level set for each of the plurality of cell portions.

A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

A method of writing data to a memory array of three-terminal memory cells includes simultaneously programming a first subset of memory cells in a first column of the memory array to a first logic level by activating a first select line of the first column and a first bit line of the first column, and simultaneously programming a second subset of memory cells in the first column to the first logic level by activating the first select line and a second bit line of the first column.

A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.

A method for forming a semiconductor memory structure includes following operations. A plurality of doped regions are formed in a semiconductor substrate. The doped regions are separated from each other. A stack including a plurality of first insulating layers and a plurality of second insulating layers alternately arranged is formed over the semiconductor substrate. A first trench is formed in the stack. The second insulating layers are replaced with a plurality of conductive layers. A second trench is formed. A charge-trapping layer and a channel layer are formed in the second trench. An isolation structure is formed to fill the second trench. A source structure and a drain structure are formed at two sides of the isolation structure.

A semiconductor memory device includes: a first semiconductor layer extending in a first direction; a first conductive layer and a second conductive layer that are arranged in the first direction and each opposed to the first semiconductor layer; a first insulating portion disposed between the first semiconductor layer and the first conductive layer, the first insulating portion containing oxygen (O) and hafnium (Hf); a second insulating portion disposed between the first semiconductor layer and the second conductive layer, the second insulating portion containing oxygen (O) and hafnium (Hf); and a first charge storage layer disposed between the first insulating portion and the second insulating portion, the first charge storage layer being spaced from the first conductive layer and the second conductive layer.

A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

Reliability of a semiconductor device including a ferroelectric memory is improved. A gate electrode of a ferroelectric memory is formed on a semiconductor substrate so as to arrange a ferroelectric film therebetween, and a semiconductor layer serving as an epitaxial semiconductor layer is formed on the semiconductor substrate on both sides of the gate electrode. The semiconductor layer is formed on a dent portion of the semiconductor substrate. At least a part of each of a source region and a drain region of the ferroelectric memory is formed in the semiconductor layer.

A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.