Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Methods, systems, and devices for a magnetic cache for a memory device are described. Magnetic storage elements (e.g., magnetic memory cells, such as spin-transfer torque (STT) memory cells or magnetic tunnel junction (MTJ) memory cells) may be configured to act as a cache for a memory array, where the memory array includes a different type of memory cells. The magnetic storage elements may be inductively coupled to access lines for the memory array. Based on this inductive coupling, when a memory value is written to or read from a memory cell of the array, the memory value may concurrently be written to a magnetic storage element based on associated current through an access line used to write or read the memory cell. Subsequent read requests may be executed by reading the memory value from the magnetic storage element rather than from the memory cell of the array.

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Methods, systems, and devices for a magnetic cache for a memory device are described. Magnetic storage elements (e.g., magnetic memory cells, such as spin-transfer torque (STT) memory cells or magnetic tunnel junction (MTJ) memory cells) may be configured to act as a cache for a memory array, where the memory array includes a different type of memory cells. The magnetic storage elements may be inductively coupled to access lines for the memory array. Based on this inductive coupling, when a memory value is written to or read from a memory cell of the array, the memory value may concurrently be written to a magnetic storage element based on associated current through an access line used to write or read the memory cell. Subsequent read requests may be executed by reading the memory value from the magnetic storage element rather than from the memory cell of the array.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.