In one embodiment, a device includes a memory cell for storing 0 or 1 as stored data, and a control circuit for reading out the stored data. The memory cell includes area C1/C3 where a cell current increases as a voltage across the cell increases, area C2/C4 where the current is larger than that in C1/C3 and the voltage decreases while the current increases, and area C5 where the current is larger than that in C2/C4 and increases as the voltage increases. The control circuit performs first processing of reading out the stored data such that the current when the data is 0 and the current when the data is 1 take values in C1/C3, and second processing of reading out the stored data such that the current when the data is 0 or the current when the data is 1 takes a value in C2/C4 or C5.

In one embodiment, a device includes a memory cell for storing 0 or 1 as stored data, and a control circuit for reading out the stored data. The memory cell includes area C1/C3 where a cell current increases as a voltage across the cell increases, area C2/C4 where the current is larger than that in C1/C3 and the voltage decreases while the current increases, and area C5 where the current is larger than that in C2/C4 and increases as the voltage increases. The control circuit performs first processing of reading out the stored data such that the current when the data is 0 and the current when the data is 1 take values in C1/C3, and second processing of reading out the stored data such that the current when the data is 0 or the current when the data is 1 takes a value in C2/C4 or C5.

In one embodiment, a device includes a memory cell for storing 0 or 1 as stored data, and a control circuit for reading out the stored data. The memory cell includes area C1/C3 where a cell current increases as a voltage across the cell increases, area C2/C4 where the current is larger than that in C1/C3 and the voltage decreases while the current increases, and area C5 where the current is larger than that in C2/C4 and increases as the voltage increases. The control circuit performs first processing of reading out the stored data such that the current when the data is 0 and the current when the data is 1 take values in C1/C3, and second processing of reading out the stored data such that the current when the data is 0 or the current when the data is 1 takes a value in C2/C4 or C5.

In one embodiment, a device includes a memory cell for storing 0 or 1 as stored data, and a control circuit for reading out the stored data. The memory cell includes area C1/C3 where a cell current increases as a voltage across the cell increases, area C2/C4 where the current is larger than that in C1/C3 and the voltage decreases while the current increases, and area C5 where the current is larger than that in C2/C4 and increases as the voltage increases. The control circuit performs first processing of reading out the stored data such that the current when the data is 0 and the current when the data is 1 take values in C1/C3, and second processing of reading out the stored data such that the current when the data is 0 or the current when the data is 1 takes a value in C2/C4 or C5.

Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and a gated diode coupled to the access device. The gated diode may include a gate stack structure that includes a direct tunneling material, a trapping material, and a blocking material.

In one form, a process of manufacturing an avalanche photodiode includes forming an insulating layer over an active region of a semiconductor substrate. A shallow terminal of the avalanche photodiode is defined using a first patterned mask. A first dopant is implanted through the first patterned mask and the insulating layer to form the shallow terminal. The first patterned mask is removed. A deep terminal of the avalanche photodiode is defined using second patterned mask. A second dopant is implanted through the second patterned mask and insulating layer to form the deep terminal of the avalanche photodiode. A respective terminal of at least one of the shallow terminal and the deep terminal is defined using a respective patterned mask that forms at least two regions that are spatially separated from each other with no implanted structure located in a space therebetween.

Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and a gated diode coupled to the access device. The gated diode may include a gate stack structure that includes a direct tunneling material, a trapping material, and a blocking material.

Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and a gated diode coupled to the access device. The gated diode may include a gate stack structure that includes a direct tunneling material, a trapping material, and a blocking material.

The present disclosure relates to an avalanche photodiode comprising a substrate having an active area. A first dopant implant in the active area forms one of an anode and the cathode of the avalanche photodiode. A second dopant implant in the active area forming the other one of the anode and the cathode of the avalanche photodiode, wherein at least one of the first and second dopant implants defines a discontinuous formation having at least one interruption.

Disclosed is a stateful logic-in-memory using silicon diodes. More particularly, the stateful logic-in-memory according to an embodiment of the present invention includes a plurality of silicon diodes, each of the silicon diodes includes an anode region, a first channel region, a second channel region and a cathode region and is included as a memory cell.