A memory system includes: a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses and performing a target refresh operation according to a row-hammer address transferred through a command/address bus; and a memory controller suitable for collecting the tracking information for the banks transferred through the plurality of data buses to generate and output the row-hammer address to the command/address bus.

A memory system includes: a memory device including at least one bank; and a memory controller suitable for: dividing the bank into a plurality of sub-regions according to an active address, generating an aging signal for the bank based on a plurality of counting values generated by counting a number of inputs of an active command for each of the sub-regions, and providing the active command, the active address, the aging signal, and a target refresh command, wherein the memory device is suitable for: generating a sampling address by sampling the active address according to the active command, and performing a target refresh operation on a word line corresponding to the sampling address according to the target refresh command while adjusting a refresh period of the bank according to the aging signal.

Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.

Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.

A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a multi-bit input local computing cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The multi-bit input local computing cell is connected to the memory cell and receives the weight via the local bit line. The multi-bit input local computing cell includes a plurality of input lines and a plurality of output lines. Each of the input lines transmits a multi-bit input value, and the multi-bit input local computing cell is controlled by the second word line to generate a multi-bit output value on each of the output lines according to the multi-bit input value multiplied by the weight.

A memory unit is controlled by a first word line and a second word line. The memory unit includes a memory cell and a multi-bit input local computing cell. The memory cell stores a weight. The memory cell is controlled by the first word line and includes a local bit line transmitting the weight. The multi-bit input local computing cell is connected to the memory cell and receives the weight via the local bit line. The multi-bit input local computing cell includes a plurality of input lines and a plurality of output lines. Each of the input lines transmits a multi-bit input value, and the multi-bit input local computing cell is controlled by the second word line to generate a multi-bit output value on each of the output lines according to the multi-bit input value multiplied by the weight.

A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.

A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.

A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.