A memory sub-system configured to use first values of a plurality of optimized read voltages to perform a first read calibration, which determines second values of the plurality of optimized read voltages. A plurality of shifts, from the first values to the second values respectively, can be computed for the plurality of optimized read voltages respectively. After recognizing a pattern in the plurality of shifts that are computed for the plurality of voltages respectively, the memory sub-system can control and/or initiate a second read calibration based on the recognized pattern in the shifts.

According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.

A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information, and a target threshold voltage level corresponding to the target memory state. Based at least on the target memory state, the memory controller determines one or more program pulses for a pre-program cycle, including voltage levels for the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information, and pre-programs the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without program verify operations. Following the pre-programming, the memory controller programs the information to the selected memory location.

A method and apparatus for calibrating read threshold for cells of a target wordline (WL) that may be conducted on a die, in a controller connected to a memory die, or both. Voltage values of one or more adjacent WL cells are read, and based on the voltage values of the adjacent cells, cells of the target WL are grouped. A read threshold calibration is carried out on each group. The calibration thresholds are then used for read operations on the cells of each distinct group of the target WL.

A storage apparatus includes an interface and storage circuitry. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple programming levels. The storage circuitry configured to program data to a first group of multiple memory cells in a number of programming levels larger than two, using a One-Pass Programming (OPP) scheme that results in a first readout reliability level. After programming the data, the storage circuitry is further configured to read the data from the first group, and program the data read from the first group to a second group of the memory cells, in a number of programming levels larger than two, using a Multi-Pass Programming (MPP) scheme that results in a second readout reliability higher than the first reliability level, and reading the data from the second group of the memory cells.

According to the one embodiment, a memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes: first and second memory cells stacked above a substrate; a first word line coupled to the first and second memory cells; a first bit line coupled to the first memory cell; and a second bit line coupled to the second memory cell. A first state read operation includes a first read operation for reading data from the first memory cell and a second read operation for reading data from the second memory cell. A first read voltage is applied to the first word line during a first period for executing the first read operation, and a second read voltage is applied to the first word line during a second period for executing the second read operation.

An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, and outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request.

A memory access module for performing memory access management of a storage device includes a plurality of storage cells. Each storage cell has a number of possible bit(s) directly corresponding to possible states of the storage cell. The memory access module further includes: sensing means for performing a plurality of sensing operations, wherein a first sensing operation corresponds to a first sensing voltage, and each subsequent sensing operation corresponds to a sensing voltage determined according to a result of the previous sensing operation; generating means for using the plurality of sensing operations to generate a first digital value and a second digital value of a storage cell; processing means for using the first and the second digital value to obtain soft information of a same bit stored in the storage cell; and decoding means for using the soft information to perform soft decoding.

The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of single-level-cell units and a plurality of triple-level cell units. The controller performs a first predetermined number of read processes on a second predetermined number of specific single-level-cell units to program data stored in the second predetermined number of specific single-level-cell units into a specific triple-level cell unit of the triple-level cell units and determines whether any of the second predetermined number of specific single-level-cell units has not been read successfully by any of the read processes when the specific triple-level cell unit cannot be read successfully.

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.