Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

Techniques for estimating raw bit error rate of data stored in a group of memory cells are described. Encoded data is read from a group of memory cells. A first population value is obtained based on a first number of memory cells in the group of memory cells having a read voltage within a first range of read voltages, each read voltage representing one or more bits of the encoded data. An estimated raw bit error rate of the data is determined to satisfy a first threshold. The determination is made using a first trained machine learning model and based in part on the first population value. A first media management operation is initiated in response to the determination that the estimated raw bit error rate satisfies the first threshold.

A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.

A block family associated with a memory device is created. The block family is associated with a threshold voltage offset bin. A set of read level voltage offsets is determined such that, applying the set of read level voltage offsets to a base read level threshold voltage associated with the block family, result in a suboptimal error rate not exceeding a maximum allowable error rate. The determined set of read level offsets is associated with the threshold voltage offset bin by updating a block family metadata.

A method can include receiving a request to read data from a memory cell of a memory device coupled with the processing device, determining a voltage distribution parameter value associated with the memory cell, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, and reading, using the determined set of read levels, data from the memory cell. The voltage distribution parameter value can be determined by identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels, and determining the voltage distribution parameter value based on the particular voltage distribution. The voltage distribution parameter value can be a voltage value that is included in the particular voltage distribution.

Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying a block family comprising a plurality of blocks of the memory device. The operations performed by the processing device further include associating the block family with a threshold voltage offset. The operations performed by the processing device further include computing an adjustment value of the threshold voltage offset, wherein the adjustment value reflects a time period that has elapsed since a triggering event and a temperature of a memory component carrying one or more blocks of the plurality of blocks.

A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.

A memory device including a plurality of memory cells, configured to perform a read operation of reading data from memory cells connected to a selected word line, and configured to apply a plurality of read voltages to the selected word line, apply a first pass voltage to unselected word lines while first read voltages for determining a program state of memory cells having a threshold voltage higher than a reference voltage among the plurality of read voltages are applied to the selected word line, and apply a second pass voltage higher than the first pass voltage to the unselected word line while second read voltages for determining a program state of memory cells having a threshold voltage lower than the reference voltage among the plurality of read voltages are applied to the selected word line.