A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.

Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

A switching element that has reduced switching voltage and leakage current and that demonstrates high reliability and low power consumption is achieved as a result of comprising: a first insulation layer in which first wiring mainly consisting of copper is embedded in a first wiring groove that opens upward; a second insulation layer which is formed on an upper surface of the first insulation layer and the first wiring and has an opening that reaches the first insulation layer and the first wiring; a first electrode which is the portion of the first wiring that is exposed from the opening; an oxygen supply layer which is formed on an upper surface of the second insulation layer, generates oxygen plasma during etching to form the opening in the second insulation layer, and remains at least in the vicinity of the opening of the upper surface of the second insulation layer; an ion conducting layer which is formed on the upper surface of the first insulation layer and the first electrode that are exposed from the opening, an inner surface of the opening of the second insulation layer, and an upper surface of the oxygen supply layer; and a second electrode that is formed on an upper surface of the ion conducting layer.

A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.

A memory comprising: a resistive-switching element having first and second electrodes separated by a layer of insulator; an energy storage component or load coupled to the resistive-switching element via a first switch; and a control circuit configured: to program the resistive-switching element to have a set state, wherein, in the set state, a filament forms a conducting path between the first and second electrodes; and, following a dissolution of the filament, to recover electrical energy, generated by the dissolution of the filament, from one of the first and second electrodes by activating the first switch.

Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.

Methods and structures for fabricating a semiconductor device that includes a reduced programming current phase change memory (PCM) are provided. The method includes forming a bottom electrode. The method further includes forming a PCM and forming a conductive bridge filament in a dielectric to serve as a heater for the PCM. The method also includes forming a top electrode.

A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

A switch device includes: a first electrode; a second electrode opposed to the first electrode; and a switch layer provided between the first electrode and the second electrode, and the switch layer includes one or more kinds of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S) and one or more kinds of first elements selected from phosphorus (P) and arsenic (As), and further includes one or both of one or more kinds of second elements selected from boron (B) and carbon (C) and one or more kinds of third elements selected from aluminum (Al), gallium (Ga), and indium (In).

The invention is directed a device for high-dimensional encoding of a plurality of sequences of quantitative data signals. The device comprises a memory crossbar array comprising a plurality of resistive devices, a first peripheral circuit connected to the memory crossbar array, and a second peripheral circuit connected to the first peripheral circuit. The device is configured to receive the plurality of sequences of quantitative data signals via a plurality of input channels and to store elements of a plurality of precomputed basis hypervectors as conductance states of the resistive devices. The plurality of basis hypervectors are bound to respective input channels. The first peripheral circuit performs a temporal encoding of n-grams of the quantitative data signals thereby creating a plurality of temporally encoded hypervectors. The second peripheral circuit performs a spatial encoding of the plurality of temporally encoded hypervectors. This creates a temporally and spatially encoded hypervector.