An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.

Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.

Methods for manufacturing memory resistor devices and memory resistor devices manufactured according to such methods. A method includes depositing a first layer of dielectric material onto a substrate comprising a first electrode; bombarding the deposited first layer with an ion beam to create one or more defects in the first layer; depositing a second electrode such that the deposited first layer is between the first electrode and the second electrode; electroforming the first layer by applying an electroforming voltage between the first electrode and the second electrode.

A method of forming bottom electrodes in a resistive memory device, can include: depositing a bottom insulator on a substrate ILD; forming vias in the substrate by patterning and etching holes in the bottom insulator and the substrate ILD; filling the holes with a via metal to form a flat via surface; depositing a bottom electrode thin film and a top insulator; defining the bottom electrode; etching the top insulator, the bottom electrode thin film, and the bottom insulator; depositing a cell plate layer having a switching layer, an anode layer, and a cap layer; patterning the cell plate layer by depositing and patterning a cell plate hard mask layer, and then etching the cell plate layer; encapsulating the cell plate layer; and forming electrical contact to the cell plate layer.

A system and method of secure communication between computing devices based on physical unclonable functions such as memories having dissolvable conductive paths is provided. The method involves enrolling a client device, the client device having a PUF such as a pristine ReRAM. The PUF is enrolled in a secure environment by reading and storing the resistances of the PUF's addressable memory cells. The cells are categorized into “rugged” and “vulnerable” categories on the basis of their resistance, the vulnerable cells being those more likely to be permanently altered during the generations of PUF responses. The rugged cells are used for the generation of PUF responses for cryptographic key generation, but the vulnerable cells may be inspected to detect unauthorized 3rd party access to the PUF.

A variable resistance nonvolatile storage device includes: a variable resistance element having a state reversibly changeable between a high resistance state and a low resistance state; and a current supply circuit that supplies the variable resistance element with a low-resistance changing current for changing the state from the high resistance state to the low resistance state. The low-resistance changing current has a waveform that includes a first period and a second period along a time axis, the second period being subsequent to the first period. The current supply circuit applies to the variable resistance element: a first current during the first period; and a second current during the second period, the second current being smaller than the first current. The first current is not zero at an end of the first period, and the second current is not zero at a start of the second period.

A variable resistance element according to an embodiment serves to change to a low resistance state or a high resistance state. The variable resistance element includes a first transition metal compound layer, a second transition metal compound layer, and a lithium ion conductor layer. The first transition metal compound layer is connected to a first electrode. The first transition metal compound layer is a metal compound containing lithium ions in lattice interstices. The second transition metal compound layer is connected to a second electrode. The second transition metal compound layer is a metal compound containing lithium ions in lattice interstices. The lithium ion conductor layer is provided between the first transition metal compound layer and the second transition metal compound layer. The lithium ion conductor layer is a solid substance that is permeable to lithium ions and is less permeable to electrons.

A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.

The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.