According to an embodiment of the present disclosure, a device and a method are provided. The device includes one or more resistive random access memory (ReRAM) elements. The device further includes a random number generator configured to generate a random number in dependence on impedance values of the one or more ReRAM elements.

The disclosure relates to secure data storage and retrieval, in particular to methods and circuits for securely storing data to reduce the possibility of leakage via side channel attacks. Embodiments disclosed include a method of storing a value comprising a series of words, the method comprising: i) combining in a series of XOR operations a word of a first portion of the value, a word of a second portion of the value and an output word of a first random number generator to provide a first combined word; ii) storing the first combined word in a shift register; and iii) repeating steps i) and ii) for each successive word of the first and second portions of the value.

An arming switch structure and method of operation. The arming switch is integrated with a reactive material erasure device and phase change memory cell array and is coupled to a tamper detection device configured to trigger a signal for conduction to the reactive material erasure device that generates heat and induces a phase change in the phase change memory cell array. Prior to packaging, the memory chip is “armed” in a high-resistance state to prevent conduction of any signal to the reactive material erasure device. After the memory chip is packaged, the Reactive Material can be “disarmed” at a chosen time or condition by applying a bias to the arming switch activation layer, thereby heating and crystallizing the arming switch material, placing it in a low resistance state. In the disarmed state, the arming switch may conduct the trigger signal from tamper detection device to the reactive material erasure device.

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

A system and method for generating encryption keys on multiple devices, without transferring the keys. At least one sender memristor is set using at least one sender setting value. At least one sender reading value is applied to the at least one sender memristor to generate at least one sender output value. A string of characters is determined from the at least one output value based on a sender table. Data is encrypted with the string of characters. The encrypted data is transmitted to a receiver through a first channel. The at least one sender setting value or the at least one sender reading value or both is transmitted to the receiver through a second channel different from the first channel. The at least one sender setting value or the at least one sender reading value or both is applied to at least one receiver memristor to generate at least one receiver output value. A receiver table is used to determine the string of characters from the at least one receiver output value. The encrypted data is decrypted with the string of characters from the receiver table.

A non-volatile memory device includes: a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit and information data recorded in the at least one data cell, is recorded in the at least one dummy cell.

A storage device that avoids unauthorized access attributable to a snapback when simultaneously accessing a plurality of memory cells includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction, and a plurality of memory cells at a position where any of the plurality of first wires and any of the plurality of second wires intersect each other. A first driving unit supplies a first voltage having any of a positive polarity and a negative polarity or a zero potential to each of the plurality of first wires. A second driving unit supplies a second voltage with a different polarity from the first voltage to any one of the plurality of second wires intersecting a first wire to which the first voltage is supplied and supplies a zero potential to a remainder of the plurality of second wires.

A system may include an array of interconnected memristors. Each memristor may include a first electrode, a second electrode, and a memristor material positioned between the first electrode and the second electrode. The system may further include a controller communicatively coupled to the array of interconnected memristors. The controller may be configured to tune the array of interconnected memristors.

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion. During a spike discharge, charge is choked by this higher resistance path. This suppresses spike current that occurs when the memory cell is selected.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.