A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.

A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.

A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The program operation includes a plurality of program loops. The control logic is configured to control the peripheral circuit to apply a program voltage to a select word line that is connected to the selected memory cells, apply a first under drive voltage that is determined based on at least one verify voltage to the select word line, and apply the at least one verify voltage to the select word line in each of the plurality of program loops. The first under drive voltage is at a lower voltage level than the at least one verify voltage.