A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.

A semiconductor memory device includes a memory block including plurality of string groups, a peripheral circuit, and control logic. The peripheral circuit performs a program operation on source select transistors included in the memory block. The control logic controls the program operation of the peripheral circuit. Each of the plurality of string groups includes at least one cell string, and the at least one cell string includes inner source select transistors located adjacent to memory cells and outer source select transistors located adjacent to a common source line. The control logic controls the peripheral circuit to perform program operations on the outer source select transistors and the inner source select transistors by an ISPP method. The control logic controls the peripheral circuit to perform a verify operation by dividing the inner source select transistors into at least two groups during the program operation of the inner source select transistors.

Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

A method of operating a non-volatile memory device is provided. The device includes a latch, a page buffer and blocks, each of which includes pages. The method includes: receiving a page command for a write operation corresponding to a page of one of the blocks; receiving a write command for writing data to the page buffer; latching preexisting latched data or random data generated as latched data; writing the latched data to a page of a new block from among the plurality of blocks that corresponds to a page address based on the write command; and repeatedly updating the page address and repeatedly writing the latched data to additional pages corresponding to each updated page address until each page of the new block has been written to.

A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information, and a target threshold voltage level corresponding to the target memory state. Based at least on the target memory state, the memory controller determines one or more program pulses for a pre-program cycle, including voltage levels for the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information, and pre-programs the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without program verify operations. Following the pre-programming, the memory controller programs the information to the selected memory location.

A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information, and a target threshold voltage level corresponding to the target memory state. Based at least on the target memory state, the memory controller determines one or more program pulses for a pre-program cycle, including voltage levels for the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information, and pre-programs the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without program verify operations. Following the pre-programming, the memory controller programs the information to the selected memory location.

A memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of string groups respectively connected to a corresponding select line, among a plurality of select lines. The peripheral circuit performs a program operation of data on the memory block. The control logic controls the program operation of the peripheral circuit. The memory block is connected to first to n-th word lines. The control logic is configured to control the peripheral circuit to perform a first program operation on a physical page, among physical pages that are included in a first string group, connected to an i-th word line, performs a second program operation on a physical page that is connected to an (i−1)-th word line, and perform a dummy program operation on a physical page that is connected to an (i+1)-th word line. Here, n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n−1.

A memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of string groups respectively connected to a corresponding select line, among a plurality of select lines. The peripheral circuit performs a program operation of data on the memory block. The control logic controls the program operation of the peripheral circuit. The memory block is connected to first to n-th word lines. The control logic is configured to control the peripheral circuit to perform a first program operation on a physical page, among physical pages that are included in a first string group, connected to an i-th word line, performs a second program operation on a physical page that is connected to an (i−1)-th word line, and perform a dummy program operation on a physical page that is connected to an (i+1)-th word line. Here, n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n−1.

The present technology relates to an electronic device. A memory device according to the present technology includes a plurality of memory cells connected to a word line, an operation controller configured to apply a first or a second read voltage to the word line and to obtain data that is stored in the plurality of memory cells through bit lines that are respectively connected to the plurality of memory cells, and a read voltage controller configured to control the operation controller to read the data that is stored in the plurality of memory cells by using the second read voltage, and to read the data that is stored in the plurality of memory cells by using the first read voltage according to the number of off cells that are counted based on the data that is read by using the second read voltage, in response to a read command.