A memory-control circuit for use in an integrated circuit is provided. The memory-control circuit includes a memory controller and a timer circuit. The memory controller performs an erase operation on a target data block of the flash memory according to an erase command from a processor, and generates an erase signal. The timer circuit starts a counting operation in response to the erase signal. In response to an intellectual-property-core circuit generating an interrupt signal, the memory controller and the timer circuit respectively suspend the erase operation and the counting operation. In response to the interrupt signal being cleared, the memory controller and the timer circuit respectively resume the erase operation and the counting operation. In response to the timer circuit having counted up to a predetermined value, the timer circuit outputs a completion signal to the memory controller to indicate that the erase operation is complete.

Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

A request to perform a secure erase operation for a memory component can be received. A voltage level that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can be associated with a program operation to place a memory cell of the memory component at another voltage level that exceeds the voltage level that is applied to the unselected wordlines of the memory component during the read operation.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.

In a nonvolatile memory writing device that writes writing data transmitted from the microcomputer to a nonvolatile memory provided outside the microcomputer, the nonvolatile memory is a nonvolatile memory in which writing is protected and the protection is disabled by an electric signal from the microcomputer to the write-protect terminal of the nonvolatile memory, the write-protect terminal is connected to the power supply of the microcomputer, and when the electric signal from the microcomputer to the write-protect terminal is interrupted, the protection is disabled, even when the data is interrupted due to a change in the power supply voltage, it is possible to prevent garbled date due to the write protection signal during the write period of the write data.

In a nonvolatile memory writing device that writes writing data transmitted from the microcomputer to a nonvolatile memory provided outside the microcomputer, the nonvolatile memory is a nonvolatile memory in which writing is protected and the protection is disabled by an electric signal from the microcomputer to the write-protect terminal of the nonvolatile memory, the write-protect terminal is connected to the power supply of the microcomputer, and when the electric signal from the microcomputer to the write-protect terminal is interrupted, the protection is disabled, even when the data is interrupted due to a change in the power supply voltage, it is possible to prevent garbled date due to the write protection signal during the write period of the write data.

Disclosed is a protection circuit of a memory in a display panel. The circuit includes: a timing controller, for outputting a first control signal; a memory, for storing software data of the timing controller; a power supply circuit, for outputting a power signal; and a monitor circuit, having three input ends and a signal output end, two input ends being respectively connected to the power supply circuit and a control signal output end, and the other one input end being input with a write control signal; the monitor circuit controls the memory to be in a write protection state when in a normal state, and controls the memory to be in a write enable state when a level state collection of the power signal, the first control signal, and the write control signal satisfies a preset level state collection.

Disclosed is a protection circuit of a memory in a display panel. The circuit includes: a timing controller, for outputting a first control signal; a memory, for storing software data of the timing controller; a power supply circuit, for outputting a power signal; and a monitor circuit, having three input ends and a signal output end, two input ends being respectively connected to the power supply circuit and a control signal output end, and the other one input end being input with a write control signal; the monitor circuit controls the memory to be in a write protection state when in a normal state, and controls the memory to be in a write enable state when a level state collection of the power signal, the first control signal, and the write control signal satisfies a preset level state collection.

A data object has a lock and a condition indicator associated with it. Based at least partly on detecting a first setting of the condition indicator, a reader stores an indication that the reader has obtained read access to the data object in an element of a readers structure and reads the data object without acquiring the lock. A writer detects the first setting and replaces it with a second setting, indicating that the lock is to be acquired by readers before reading the data object. Prior to performing a write on the data object, the writer verifies that one or more elements of the readers structure have been cleared.