A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware that includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings. When determining, based on a reference array, that the data out message will change the mode parameters which cannot be rewritten in the first mode page setting, the controller rejects to change the mode parameters which cannot be rewritten in the first mode page setting. The reference array stores a rewriteable setting for each bit of the first mode page setting.

A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware that includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings. When determining, based on a reference array, that the data out message will change the mode parameters which cannot be rewritten in the first mode page setting, the controller rejects to change the mode parameters which cannot be rewritten in the first mode page setting. The reference array stores a rewriteable setting for each bit of the first mode page setting.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD transistors. With the at least one first unselected partial SGD transistor electrically floating, the method continues with reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect.

A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD transistors. With the at least one first unselected partial SGD transistor electrically floating, the method continues with reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.