The present technology includes a memory device. The memory device includes memory cells, page buffers configured to store sensed data obtained from the memory cells, a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code, and output a pass signal or a fail signal according to a comparison result, and a fail bit manager configured to increase an allowable number of fail bits included in the allowable fail bit code until the pass signal is output from the current sensing circuit, change the allowable fail bit code according to the allowable number of fail bits, and provide the allowable fail bit code to the current sensing circuit.

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

The present technology relates to an electronic device. A memory device that controls a voltage applied to each line to prevent or mitigate a channel negative boosting phenomenon during a sensing operation includes a memory block connected to a plurality of lines, a peripheral circuit configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines, and control logic configured to control voltages applied to drain select lines, source select lines, and word lines between the drain select lines and the source select lines among the plurality of lines, during the sensing operation and an equalizing operation performed after the sensing operation. The control logic controls a voltage applied to an unselected drain select line according to whether a cell string is shared with a selected drain select line among the drain select lines, during the sensing operation.

The present technology relates to an electronic device. A memory device that controls a voltage applied to each line to prevent or mitigate a channel negative boosting phenomenon during a sensing operation includes a memory block connected to a plurality of lines, a peripheral circuit configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines, and control logic configured to control voltages applied to drain select lines, source select lines, and word lines between the drain select lines and the source select lines among the plurality of lines, during the sensing operation and an equalizing operation performed after the sensing operation. The control logic controls a voltage applied to an unselected drain select line according to whether a cell string is shared with a selected drain select line among the drain select lines, during the sensing operation.

A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.

A system includes a memory device storing groups of managed units and a processing device operatively coupled to the memory device. The processing device is to, during power on of the memory device, perform including: causing a read operation to be performed at a subset of a group of managed units; determining a bit error rate related to data read from the subset of the group of managed units; and in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.

A system comprising includes a memory device having memory cells a processing device, operatively coupled to the memory device. The processing device is to perform operations including: determining a length of time the memory device has been powered off; and in response to determining that the length of time satisfies a threshold value: for each of multiple groups of memory cells, asserting a corresponding flag; determining, based on the length of time, one or more adjusted demarcation voltages to be used in reading a state of the multiple groups of memory cells; and storing the one or more adjusted demarcation voltages for use in performing memory operations.