A storage system has a memory with a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block. The storage system repurposes the partially-bad SLC block as a non-volatile read cache for data stored in the MLC block (e.g., cold data that is read relatively frequently) to improve performance of host reads. Because the original version of the data is still stored in the MLC block, the original version of the data can be read if there is an error in the copy of the data stored in the partially-bad SLC block, thus avoiding the need for extensive error-correction handling to account for the poor reliability of the partially-bad SLC block.

A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information, and a target threshold voltage level corresponding to the target memory state. Based at least on the target memory state, the memory controller determines one or more program pulses for a pre-program cycle, including voltage levels for the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information, and pre-programs the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without program verify operations. Following the pre-programming, the memory controller programs the information to the selected memory location.

The present technology relates to an electronic device. A memory device according to the present technology includes a plurality of memory cells connected to a word line, an operation controller configured to apply a first or a second read voltage to the word line and to obtain data that is stored in the plurality of memory cells through bit lines that are respectively connected to the plurality of memory cells, and a read voltage controller configured to control the operation controller to read the data that is stored in the plurality of memory cells by using the second read voltage, and to read the data that is stored in the plurality of memory cells by using the first read voltage according to the number of off cells that are counted based on the data that is read by using the second read voltage, in response to a read command.

A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic to perform memory erase operations including: performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step; in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and resuming the true erase sub-operation at an end of the subsequent pulse-step period.

Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation for storing data in selected memory cells among the plurality of memory cells, and a control logic circuit configured to control the peripheral circuit to form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively, wherein the control logic controls the peripheral circuit to perform a main verify operation for any one of the target program states of the selected memory cells when a pre-verify operation for the any one of the target program states has passed.

An operating method of a semiconductor device including a controller and a non-volatile memory device operating under control of the controller is provided. The operating method includes determining, by the controller, whether the non-volatile memory device satisfies a block program condition; based on the non-volatile memory device satisfying the block program condition, performing a block program operation a plurality of times; and based the non-volatile memory device not satisfying the block program condition, performing an erase operation.

An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.

Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.

A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit, a verification circuit and a control circuit. During a sample period of a verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the verification circuit and convert the n M-th reference currents into n reference voltages. During a verification period of the verification action, the control circuit controls n multi-level memory cells of a selected row of the cell array to generate n cell currents to the verification circuit and convert the n cell currents into n sensed voltages. The n verification devices generate the n verification signals according to the reference voltages and the sensed voltages. Accordingly, the control circuit judges whether the n multi-level memory cells have reached an M-th storage state.

Exemplary methods, apparatuses, and systems include receiving a plurality of read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets. The size of the current set is a first number of read operations. An aggressor read operation is selected from the current set. A data integrity scan is performed on a victim of the aggressor and a first indicator of data integrity is determined based on the first data integrity scan. A size of a subsequent set of read operations is set to a second number, which less than the first number, based on the indicator of data integrity.