In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.

A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.

A memory circuit includes a first programming device, a first circuit branch and a second circuit branch. The first programming device includes a first control terminal coupled to a first word line, and a first connecting end. The first circuit branch includes a first diode, and a first fuse element coupled to the first diode. The second circuit branch includes a second diode, and a second fuse element coupled to the second diode. The first circuit branch and the second circuit branch are coupled to the first connecting end of the first programming device.

The invention provides a multi-Vt vertical power device and a method of making the same. Through patterning a contact mask, a contact structure array having a shared trench gate structure may be formed, and different traversal gaps between an edge of a contact portion of a second conductivity type and an edge of a trench may be formed in the contact structure array. As such, multi-Vt vertical states may be implemented for storing information. The present invention allows making a multi-Vt vertical power device having different Vt's to be capable to store information without additional process steps. Therefore, with respect to the present invention, the process is simple, cost is low, and application field is wide; number of Vt varies to store multi-bit digital information or analog information in the power device; the built-in multi-Vt power MOSFET and IGBT are adapted not only for the high power applications but also for information storage.

This invention provides a multi-Vt vertical power device and a method of making the same. Through a contact mask, a contact structure array having a shared trench gate structure may be formed, the same traversal gaps between an edge of a contact portion of a second conductivity type of the same set and an edge of a trench may be formed in the contact structure array, and different traversal gaps between an edge of the contact portion of the second conductivity type of different sets and an edge of the trench may be formed in the contact structure array. As such, multi-Vt states may be implemented for storing digital information. The present invention allows making a multi-Vt vertical power device having a number of Vt's to be capable of storing same number of bits digital information without additional process steps. Therefore, the built-in multi-Vt power MOSFET and IGBT are adapted not only for the high power applications but also for information storage; simultaneous reading multi-bit information stored in the multi-Vt vertical power device is provided with scanning a voltage of a shared gate and constructing a transconductance.

A device includes a programmable ROM circuit, an address circuit, and a processor. The programmable ROM circuit includes multiple physically contiguous pairs of bit-cells, each pair of bit-cells includes an active layer trace extending continuously across both of the bit-cells, each pair of bit-cells comprises a shared contact layer point when the pair of bit-cells is programmed to a value of one and no shared contact layer point when the pair of bit-cells is programmed to a value of zero. The address circuit is coupled to the programmable ROM circuit and configured to address only a first bit-cell of each pair of bit-cells. The processor is coupled to the address circuit and the programmable ROM circuit and configured to use the address circuit to read data from one or more pairs of bit-cells of the programmable ROM circuit.

A device includes a programmable ROM circuit, an address circuit, and a processor. The programmable ROM circuit includes multiple physically contiguous pairs of bit-cells, each pair of bit-cells includes an active layer trace extending continuously across both of the bit-cells, each pair of bit-cells comprises a shared contact layer point when the pair of bit-cells is programmed to a value of one and no shared contact layer point when the pair of bit-cells is programmed to a value of zero. The address circuit is coupled to the programmable ROM circuit and configured to address only a first bit-cell of each pair of bit-cells. The processor is coupled to the address circuit and the programmable ROM circuit and configured to use the address circuit to read data from one or more pairs of bit-cells of the programmable ROM circuit.

An apparatus for reading a bit of a memory array includes a bit cell column, voltage enhancement circuitry, and control circuitry. The voltage enhancement circuitry is configured to couple a bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of a plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node and determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.

A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.