An OTP memory device includes a substrate, a first transistor, a second transistor, a first word line, second word line, and a bit line. The first transistor includes a first gate structure, and first and second source/drain regions on opposite sides of the first gate structure. The second transistor is operable in an inversion mode, and the second transistor includes a second gate structure having more work function metal layers than the first gate structure of the first transistor, and second and third source/drain regions on opposite sides of the second gate structure. The first word line is over and electrically connected to the first gate structure of the first transistor. The second word line is over and electrically connected to the second gate structure of the second transistor. The bit line is over and electrically connected to the first source/drain region of the first transistor.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first dielectric layer on a substrate; first/second upper short axis portions extending along a first direction, separated from each other, and on the first dielectric layer; a common source region in the substrate and adjacent to the first/second upper short axis portions; a first branch drain region in the substrate, adjacent to the first upper short axis portion, and opposite to the common source region; a second branch drain region in the substrate, adjacent to the second upper short axis portion, and opposite to the common source region; and a top electrode on the first dielectric layer and topographically above the first branch drain region and the second branch drain region. The top electrode, the first dielectric layer, and the first/second branch drain regions together configure a programmable unit.

Disclosed herein are related to a memory array including one-time programmable (OTP) cells. In one aspect, the memory array includes a set of OTP cells including a first subset of OTP cells connected between a first program control line and a first read control line. Each OTP cell of the first subset of OTP cells may include a programmable storage device and a switch connected between the first program control line and the first read control line. The first program control line may extend towards a first side of the memory array along a first direction, and the first read control line may extend towards a second side of the memory array facing away from the first side of the memory array.

A re-programmable integrated circuit (IC) includes a plurality of non-volatile memory elements, each including a fuse portion initially configured to have either a first resistance value or a second resistance value. Re-programming circuitry includes a controllable element coupled to each fuse portion and selectively operable to cause an electrical current to flow through the fuse portion sufficient to cause that fuse portion to transition to an altered state having a resistance value greater than the first and second resistance values. Reference resistance circuitry is configurable between an initial state and a re-programmed state. Read circuity determines the logic state of each of the memory elements using a comparator circuit operable to sense the resistance value of a fuse portion and the reference resistance, whether in the initial or re-programmed state, wherein the logic state of a memory element is a function of whether the resistance value of the fuse portion is greater than or less than the reference resistance.

A memory device includes a plurality of resistive random access memory (RRAM) cells commonly connected between a bit line (BL) and a source line (SL). Each of the RRAM cells includes a resistor, a first transistor, and a second transistor coupled to each other in series, with the resistor connected to the BL and the second transistor connected to the SL. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage, the first threshold voltage being less than the second threshold voltage.

An integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer and coupled between the transistor and a first data line. The second fuse element is formed in the second conductive layer and coupled between the transistor and a second data line. The first fuse element and the second fuse element are disposed at a same side of the transistor.

A 3D device, the device including: a first level including logic circuits; a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the first level includes at least one voltage regulator circuit.

According to one embodiment, a memory device includes: a memory cell array including a first and a second array; a fuse circuit to hold first data; and a control circuit to control a replacement process on the first and second arrays based on the first data. When a first address in a first direction in the first array is supplied, the fuse circuit transfers the first data corresponding to the first address to the control circuit, and when a second address in a second direction in the first array is supplied after the first data is transferred, the control circuit accesses one of the first and second arrays based on a comparison result for the second address and the first data.

An anti-fuse device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a salicide layer formed on a first portion of the gate electrode such that a second portion of the gate electrode omits the salicide layer, wherein a hard breakdown of at least a portion of the gate insulating film at a time of programming the anti-fuse device.

Embodiments provide an anti-fuse storage layout and a circuit thereof, and an anti-fuse memory and a design method thereof. The anti-fuse storage layout includes: active regions extending along a first direction and being discretely arranged along a second direction, each of the active regions including at least two memory cell regions arranged along the first direction, each of the at least two memory cell regions including an anti-fuse region and a control region arranged along the first direction, and the control regions of the adjacent memory cell regions being adjacent to each other along the first direction; a word line region extending along the second direction and intersecting with the control region; an electrical connection region extending along the second direction and intersecting with the anti-fuse region; and a programming control region extending along a third direction and being positioned at one side of the corresponding active region.