A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

The present disclosure relates to a shift register and a display apparatus, wherein the shift register comprising an input module, a pull-down module, an inversion module and a first pull-up module; wherein, the input module supplies an input signal voltage to a pull-down node in response to a first clock signal, wherein the pull-down node is an output node of the input module; the pull-down module stores the input signal voltage and supplies a second clock signal to an output terminal in response to the pull-down node; the inversion module supplies a positive power supply voltage or a negative power supply voltage to a first pull-up node in response to the pull-down node; and the first pull-up module supplies the positive power supply voltage to the output terminal in response to the first pull-up node. Some or all the floating nodes in the shift register are not floated any more by improvement; as an alternative, the sources/drains of the TFTs subjected to the effects of the floating nodes are controlled so that the output stability of the shift register is improved.

An n-th driving stage of a gate driving circuit includes a first control transistor being configured to increase a voltage of a first node to a first voltage, a control capacitor having one end connected to the first node, a second control transistor being configured to increase the first voltage of the first node to a second voltage that is higher than the first voltage, a third control transistor being configured to increase a voltage of a second node to a third voltage when being turned on according to the voltage applied to the first node, and an output transistor being configured to output a gate signal of the n-th driving stage when being turned on according to the voltage applied to the second node.

A shift register is proposed, comprising: a first control module connected to an ON voltage access terminal and a first node, for controlling whether to output an ON voltage and a first control signal to the first node; a second control module connected to the ON voltage access terminal, a second node and an output terminal, for controlling whether to output the ON voltage and a voltage of the output terminal to the second node; an output module connected to the first node, the second node, the output terminal, an OFF voltage access terminal, and the ON voltage access terminal, for inputting the ON or OFF voltage to the output terminal according to voltages of the first and second nodes; and an input module connected to an input terminal, for controlling whether to input a signal of the input terminal to the first and second control modules.

A gate on array (GOA) circuit for used in an LCD includes GOA units connected in cascade. An Nth GOA unit includes an Nth stage-transmittance circuit, an Nth Q-node controlling circuit, an Nth P-node controlling circuit, an Nth outputting circuit, and a first switch circuit where N is a positive integer. The first switch circuit connected to the Nth scanning line, for inputting an enabling signal to the Nth scanning line before the LCD shows images so as to turn on a TFT in a pixel which the Nth scanning line is connected to. The benefit of the function is that the display does not leak electricity when the black screen is woken up and that the stability of the circuit is enhanced at the same time.

A GOA substrate includes N shift register units. The first stage shift register unit outputs a scan signal pulse based on a first clock signal and a start signal. The last stage shift register unit outputs a scan signal pulse based on Mth clock signal and the start signal. The start signal has a pulse width starting from a falling edge of the Mth clock signal of the last stage shift register unit when scanning a first frame, and ending at a rising edge of the first clock signal of the first stage shift register unit when scanning a second frame. Since the first and last shift register units are used to drive a scan signal pulse based on the start signal, the present invention reduces the number of wires needed to transmit start signals and simplifies the complexity of the layout design.

The embodiments of the present disclosure provide a shift register unit, a gate driving circuit and a driving method thereof, and a display device. The shift register unit, includes two transfer gate modules (211, 212), two NOR gate modules (NOR1, NOR2), two AND gate modules (AND3, AND4), two capacitor modules (241, 241), and two inverter modules (225, 227). The shift register unit provided in the present disclosure can make the layout area occupied by the corresponding gate driving circuit reduce greatly as compared with that occupied by the gate driving circuit in the prior art, which facilitates border narrowing of the corresponding display device.

A stage circuit includes a first substage circuit unit connected to first through third input terminals receiving a start signal, a first clock signal, and a second clock signal, respectively. The first substage circuit unit generates first and second operation signals based on the start signal and the first and second clock signals, and supplies a first scan signal to a first output terminal based on the first and second operation signals. The stage circuit further includes a second substage circuit unit connected to the third input terminal and a fourth input terminal receiving a third clock signal. The second substage circuit unit supplies a second scan signal to a second output terminal based on the first and second operation signals, the second clock signal, and the third clock signal. The first and second scan signals include a pulse of a low voltage level and a high voltage level, respectively.

It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small. A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line. The scan line driver circuit includes a second transistor and a capacitor for holding a voltage between a gate electrode layer of the second transistor and a source electrode layer of the second transistor. The source electrode of the second transistor is connected to the scan line.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.