A shift register unit and a control method thereof, a gate drive device including the shift register unit, and a display device. The shift register unit includes: an input module, a pull-up module, a first pull-down control signal generation module, controlling, in the period that a first signal is high level, potential of a first pull-down control node according to a drive input signal and potential of a pull-up control node; a second pull-down control signal generation module, controlling, in the period that a second signal is high level, potential of a second pull-down control node according to the drive input signal and the potential of the pull-up control node, the first signal and the second signal alternatively becoming high level; and a pull-down module, pulling down a drive output signal according to the potential of the first pull-down control node and the potential of the second pull-down control node.

A sensing driving circuit and a display device including the same are disclosed. In one aspect, the sensing driving circuit includes a plurality of stages configured to respectively output a plurality of sensing signals and including a (K)th stage and a (K+1)th stage. The (K)th stage includes a shift register configured to provide a (K)th carry signal to the (K+1)th stage; and a masking buffer configured to output a (K)th sensing signal. The masking buffer includes a first input circuit configured to provide i) an input signal to a first node based on a node driving signal and ii) a first power voltage to a second node based on the input signal and the node driving signal. The masking buffer also includes a node masking circuit configured to supply the first power voltage to the first node based on a masking signal.

A signal processing method includes the following operations: receiving an input signal and analyzing the input signal to generate a plurality of bit codes by a signal receiving circuit; temporarily storing a first part of the plurality of bit codes according to a time sequence by a shift register and starting a decoder when the shift register is full; and performing a boundary calibration according to the first part of the plurality of bit codes by the decoder when the first part of the plurality of bit codes meets a decoding table rule and a boundary detection rule.

The present disclosure discloses a shift register unit, a gate drive circuit, and a display device. The shift register unit includes first to twelfth switch elements, a first capacitor, and a second capacitor. The first switch element switches on in response to an input signal, the second switch element switches on in response to a first clock signal, the third, the ninth and the twelfth switch elements switch on in response to a signal of the second node, the fourth switch element switches on in response to a signal of the first node, and the fifth, the seventh and the eleventh switch elements switch on in response to a second clock signal.

In accordance with an embodiment of the present disclosure, a semiconductor device may be provided. The semiconductor device may semiconductor device may be configured to store a bank address applied to an active signal from among command signals, and may perform a read or a write operation using the stored bank address based on activation of a command signal.

A pulse generation circuit is configured with a plurality of transistors of a single conductivity type. The pulse generation circuit includes: an output unit including a current limiting element configured to supply, by a predetermined current, a first voltage from a first power supply line supplied with the first voltage to an output terminal, the output unit being configured to perform a bootstrap operation that outputs the first voltage to the output terminal in response to a received input signal; and an output control unit configured to initiate the bootstrap operation when the output terminal transitions to the first voltage, and after the output terminal transitions to the first voltage, terminate the bootstrap operation and perform control so as to output the first voltage from the current limiting element to the output terminal.

A shiftable memory supporting in-memory data structures employs built-in data shifting capability. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data from a first location to a second location within the memory. The shiftable memory further includes a data structure defined on the memory to contain data comprising the contiguous subset. The built-in shifting capability of the memory to facilitate one or more of movement of the data, insertion of the data and deletion of the data within the data structure.

There are presented a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register includes a first feedback module and a pull-down module, wherein the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register. The shift register is used to enhance noise resistance capability of the shift register.

A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.

A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.