The present disclosure is related to a shift register unit. The shift register unit may include a shift register circuit and N output control circuits, wherein N is an integer larger than or equal to 2. The shift register circuit may be respectively electrically connected with an input signal terminal, a clock signal terminal, and an output node. Among the N output control circuits, an i-th output control circuit may be respectively electrically connected with an i-th control signal terminal of N control signal terminals, the output node, and an i-th gate line of N gate lines. i is a positive integer of smaller than or equal to N. The shift register unit may be configured to sequentially output a gate driving signal to the N gate lines respectively under control of the N control signal terminals.

A network device includes a linear feedback shift register circuit and a value updating circuit. The linear feedback shift register circuit is configured to perform an auto crossover mechanism according to at least one clock signal and a plurality of first bits, in order to control at least one port of a first interface circuit to connect with a second interface circuit. The value updating circuit is configured to perform at least one of a plurality of operations according to exclusive information. The plurality of operations includes: generating a plurality of initial values, in which the value updating circuit is configured to utilize the plurality initial values to update at least one partial bits of the plurality of first bits; or setting a period of the at least one clock signal, in which the exclusive information includes operational information or production information of the network device.

A pseudo-random sequence generator for use within a universal lidar system and its corresponding method of operation. The pseudo-random sequence generator uses synchronized shift registers that are in series Binary adders are provided. The signal output of each of the shift registers is tapped and directed to the binary adders. High-speed switches are provided between the shift registers and the binary adders. The switches are programmed to connect only two of the shift registers to the binary adders for each of the pseudo-random patterns being generated. The binary adders generate an output signal that is received by the first shift register. The signal propagates through all the shift registers to the last shift register. The last shift register outputs a pseudo-random sequence.

The present disclosure is related to a shift register unit. The shift register unit may include a shift register circuit and N output control circuits, wherein N is an integer larger than or equal to 2. The shift register circuit may be respectively electrically connected with an input signal terminal, a clock signal terminal, and an output node. Among the N output control circuits, an i-th output control circuit may be respectively electrically connected with an i-th control signal terminal of N control signal terminals, the output node, and an i-th gate line of N gate lines. i is a positive integer of smaller than or equal to N. The shift register unit may be configured to sequentially output a gate driving signal to the N gate lines respectively under control of the N control signal terminals.

A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.

Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.

Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register (pSR) according to present disclosure receives a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal)=1. The loadable Shift Register with programmable load location (pSRL) is configured to obtain L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and wherein the pSRL is adapted to perform loading and shifting of data D based at least on the L, S, LL, and p values.

Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register (pSR) according to present disclosure receives a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal)=1. The loadable Shift Register with programmable load location (pSRL) is configured to obtain L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and wherein the pSRL is adapted to perform loading and shifting of data D based at least on the L, S, LL, and p values.

An object of the present invention is to suppress deterioration in the thin film transistor. A plurality of pulse output circuits each include first to eleventh thin film transistors is formed. The pulse output circuit is operated on the basis of a plurality of clock signals which control each transistor, the previous stage signal input from a pulse output circuit in the previous stage, the next stage signal input from a pulse output circuit in the next stage, and a reset signal. In addition, a microcrystalline semiconductor is used for a semiconductor layer serving as a channel region of each transistor. Therefore, degradation of characteristics of the transistor can be suppressed.

Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (LSB) and most significant bit (MSB) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.