Disclosed are a readout circuit, a signal quantizing method, a signal quantizing device, and a computer device. The readout circuit includes: a signal sampler, including a plurality of channels; a plurality of integrators, connected to the plurality of channels and having a one-to-one releationship with the plurality of channels; a signal processor, including a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively; and an analog-digital converter. An input of the analog-digital converter is connected to an output of the first operational amplifier.

A system includes an input voltage source, a linear regulator coupled to the input voltage source, and a load coupled to an output of the linear regulator. The linear regulator includes an error amplifier coupled to a control terminal of a switch; and a control circuit coupled to the error amplifier and configured to provide a reference voltage to the error amplifier. The control circuit includes a mode selection circuit with a slow loop configured to sample a load current and with a fast loop configured to detect an output voltage error signal. The mode selection circuit is configured to adjust a mode of the control circuit between a continuous power mode and a duty cycle power save mode based on the sampled load current and the output voltage error signal.

An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

A buffer circuit includes a first differential signal input, a second differential signal input, a first source follower circuit, and a second source follower circuit. The first source follower circuit includes a first signal output, and a first input transistor. The first input transistor is coupled to the first differential signal input, and is configured to drive the first signal output. The second source follower circuit includes a second signal output, a second input transistor, and a cascode transistor. The second input transistor is coupled to the second differential signal input, and is configured to drive the second signal output. The cascode transistor is coupled to the second input transistor and the first signal output, and is configured to compensate for non-linearity of the second input transistor based on an output signal provided at the first signal output.

A switch circuit for use in a single-ended switched-capacitor circuit for front-end circuitry of a sensor device is disclosed. The switch circuit comprises a first transistor and a second transistor having a same channel-type as the first transistor. A first node is connected to a source of the first transistor and a drain of the second transistor and a second node is connected to a drain of the first transistor and a source of the second transistor. Also disclosed is a sampling circuit comprising the switch circuit and a sampling capacitor, wherein the switch circuit is configurable to electrically couple the sampling capacitor to an integrator circuit or to a voltage reference. An integrated circuit device and a light to frequency converter or light sensor comprising the switch circuit is also disclosed.

Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.

According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.

A multiply-and-accumulate (MAC) circuit having a plurality of compute-in-memory bitcells is configured to multiply a plurality of stored weight bits with a plurality of input bits to provide a MAC output voltage. A successive approximation analog-to-digital converter includes a capacitive-digital-to-analog-converter (CDAC) configured to subtract a bias voltage from the MAC output voltage to provide a CDAC output voltage. A comparator compares the CDAC output voltage to a fixed reference voltage.