A device for limiting a power loss during the sampling of a digital signal is illustrated. The device comprises a circuit disposed in the signal path of the digital signal, the circuit being configured to reduce a current flow along the signal path in response to a control signal which indicates a sampling pause.

A LIDAR device includes an input node, an output node, and a sample-and-convert circuit. The input node receives a photodetector signal, and the output node generates an output signal indicating a light intensity value of the photodetector signal. The sample-and-convert circuit includes a number of detection channels coupled in parallel between the input node and the output node. In some aspects, each of the detection channels may be configured to sample a value of the photodetector signal during the sample mode and to hold the sampled value during the convert mode using a single capacitor.

Disclosed is a high-speed track-and-hold device including a buffer stage circuit including a PMOS source follower and a post linear circuit, and a sampling stage circuit that is responsible for supplying a source voltage (V.sub.SS) to the buffer stage circuit and that is arranged so that a switch connected to a gate is connected to the source voltage (V.sub.SS) and the NMOS transistor of a sampling stage is turned off in hold operation.

A current sample-and-hold circuit and a sensor, are provided. The current sample-and-hold circuit is used for offsetting a background photocurrent of a photodiode, and includes a capacitor and a first transconductance amplifier which has adjustable transconductance and outputs a sampled current to the photodiode to offset the background photocurrent of the photodiode. One end of the capacitor is connected with a power supply, the other end of the capacitor is connected with one end of the first transconductance amplifier; and the other end of the first transconductance amplifier is connected with the photodiode to output the sampled current to the photodiode. When the background photocurrent of the photodiode is increased, a change of a voltage of the capacitor within a large range can be avoided by increasing the transconductance of the first transconductance amplifier, so that the current sample-and-hold circuit can offset a larger background photocurrent.

The track-and-hold circuit includes a switching circuit and a plurality of storage devices. The switching circuit responsive to an input signal applies a representation of the input signal to the storage devices in a track mode and blocks a signal path between the input signal and the storage device in a hold mode such that a transition from the track mode to a hold mode causes the storage devices to store a time sample of the input signal. An acquisition glitch suppression circuit includes a replica amplifier coupled to the switching circuit that senses a differential voltage across the storage devices. A switched clamping circuit clamps inputs of the switching circuit to the sensed differential voltage in the hold mode such that the initial condition of switching transistors of the switching circuit are approximately identical prior to a hold-to-track transition to mitigate differential acquisition glitch.

The present disclosure relates to a current memory circuit for minimizing clock feedthrough, the circuit including: a first memory capacitor implemented as a first conductive type MOS; a second memory capacitor implemented as a second conductive type MOS; and a dummy capacitor for connecting the first memory capacitor and the second memory capacitor to each other, wherein the first memory capacitor and the second memory capacitor are current mirrors. Accordingly, a current memory circuit with a more accurate performance, low power consumption, and an integration capability can be provided.

A current sampling and holding circuit is disclosed. The current sampling and holding circuit includes: a canceling circuit, connected in series between a VDD terminal and a current sensor, being conducted according to a first enable signal, and configured to output a current to cancel a direct-current component in the current sensor; and a mirroring circuit, connected in parallel between the VDD terminal and a ground voltage with the canceling circuit and the current sensor connected in series, and being conducted according to a second enable signal inverse to the first enable signal, and configured to perform current transfer according to a current difference between a mirror current of a shunt current and an output current of the current sensor. According to the present application, the setup speed of the current sampling and holding circuit is improved, and the noise output by the current sampling and holding circuit is reduced.

The present disclosure relates to a current memory circuit for minimizing clock feedthrough, the circuit including: a first memory capacitor implemented as a first conductive type MOS; a second memory capacitor implemented as a second conductive type MOS; and a dummy capacitor for connecting the first memory capacitor and the second memory capacitor to each other, wherein the first memory capacitor and the second memory capacitor are current mirrors. Accordingly, a current memory circuit with a more accurate performance, low power consumption, and an integration capability can be provided.

A current sampling and holding circuit is disclosed. The current sampling and holding circuit includes: a canceling circuit, connected in series between a VDD terminal and a current sensor, being conducted according to a first enable signal, and configured to output a current to cancel a direct-current component in the current sensor; and a mirroring circuit, connected in parallel between the VDD terminal and a ground voltage with the canceling circuit and the current sensor connected in series, and being conducted according to a second enable signal inverse to the first enable signal, and configured to perform current transfer according to a current difference between a mirror current of a shunt current and an output current of the current sensor. According to the present application, the setup speed of the current sampling and holding circuit is improved, and the noise output by the current sampling and holding circuit is reduced.

The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.