A static random-access memory and a fault detection circuit thereof are provided. The fault detection circuit includes: a bit line coupling circuit, coupled between a first bit line and a second bit line, wherein the bit line coupling circuit is adapted to use a bit line with a lower potential between the first bit line and the second bit line to couple a bit line with a higher potential between the first bit line and the second bit line to a floating low potential in response to performing the data write operation on the memory cell in a test mode by the write circuit; and a fault determining circuit, adapted to, in response to the memory cell being at the test mode, obtain and compare write data and read data corresponding to the write data, to determine whether the SRAM has a Data Retention Fault based on a comparison result.

A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values by modifying a first trim value of the baseline trim values; instructing each memory sub-system to perform seasoning operations using the first modified set of trim values; responsive to determining that each memory sub-system passed failure scanning operations, generating a second modified set of trim values; instructing each memory sub-system to perform seasoning operations using the second modified set; responsive to determining that a memory sub-system failed the failure scanning operations, determining whether the failed memory sub-system is defective; and responsive to determining that the failed memory sub-system does is not defective, storing the first modified trim values for the set of form factors.

A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values by modifying a first trim value of the baseline trim values; instructing each memory sub-system to perform seasoning operations using the first modified set of trim values; responsive to determining that each memory sub-system passed failure scanning operations, generating a second modified set of trim values; instructing each memory sub-system to perform seasoning operations using the second modified set; responsive to determining that a memory sub-system failed the failure scanning operations, determining whether the failed memory sub-system is defective; and responsive to determining that the failed memory sub-system does is not defective, storing the first modified trim values for the set of form factors.

A scan network configured to transport repair information between memories and a controller for a non-volatile storage device comprises: repair registers coupled in parallel to repair information generation circuitry for one of the memories and segment selection devices that divide the repair registers into repair register segments. Each of the segment selection devices comprises: a storage element configured to store a segment selection bit and segment selection bit generation circuitry configured to generate the segment selection bit based on the repair information. Each of the segment selection devices is configurable to include or not include the corresponding repair register segment in a scan path of the scan network in a shift operation based on the segment selection bit.

A scan network configured to transport repair information between memories and a controller for a non-volatile storage device comprises: repair registers coupled in parallel to repair information generation circuitry for one of the memories and segment selection devices that divide the repair registers into repair register segments. Each of the segment selection devices comprises: a storage element configured to store a segment selection bit and segment selection bit generation circuitry configured to generate the segment selection bit based on the repair information. Each of the segment selection devices is configurable to include or not include the corresponding repair register segment in a scan path of the scan network in a shift operation based on the segment selection bit.

Method for testing an integrated circuit device (1), by defect modelling of the integrated circuit device (1), fault modelling of the integrated circuit device (1) based on the information obtained from the defect modelling, test development based on information obtained from the fault modelling, and executing the test on the integrated circuit device (1). Defect modelling of the integrated circuit device (1) comprises executing a physical defect analysis (10) of the integrated circuit device (1) to provide a set of effective technology parameters (Tp.sub.eff) modified from a set of defect-free technology parameters (Tp.sub.df) associated with the integrated circuit device (1), and executing an electrical modelling (11) of the integrated circuit device (1) using the set of effective technology parameters (Tp.sub.eff) to provide a defect-parametrized electrical model (16; 17) based on a defect-free electrical model of the integrated circuit device (1). The present methods allow parts-per-billion testing capabilities.

Method for testing an integrated circuit device (1), by defect modelling of the integrated circuit device (1), fault modelling of the integrated circuit device (1) based on the information obtained from the defect modelling, test development based on information obtained from the fault modelling, and executing the test on the integrated circuit device (1). Defect modelling of the integrated circuit device (1) comprises executing a physical defect analysis (10) of the integrated circuit device (1) to provide a set of effective technology parameters (Tp.sub.eff) modified from a set of defect-free technology parameters (Tp.sub.df) associated with the integrated circuit device (1), and executing an electrical modelling (11) of the integrated circuit device (1) using the set of effective technology parameters (Tp.sub.eff) to provide a defect-parametrized electrical model (16; 17) based on a defect-free electrical model of the integrated circuit device (1). The present methods allow parts-per-billion testing capabilities.

Disclosed is a method for grading memory modules comprising: a testing step which applies at least one test procedure to test a memory, each test procedure is provided with a reliability test; and a grading step which grades the memory into corresponding grade level according to test results of said at least one test procedure, and each test result includes a reliability test result wherein the reliability test has the following steps in sequence: performing a data-writing operation on the memory, wherein the data-writing operation is an operation that writes data to the memory; stopping electric charging the memory; halting a predetermined time period; electric charging the memory; checking data integrity of the memory; and generating the reliability test result according to the data integrity.

Disclosed is a method for grading memory modules comprising: a testing step which applies at least one test procedure to test a memory, each test procedure is provided with a reliability test; and a grading step which grades the memory into corresponding grade level according to test results of said at least one test procedure, and each test result includes a reliability test result wherein the reliability test has the following steps in sequence: performing a data-writing operation on the memory, wherein the data-writing operation is an operation that writes data to the memory; stopping electric charging the memory; halting a predetermined time period; electric charging the memory; checking data integrity of the memory; and generating the reliability test result according to the data integrity.

A read threshold voltage can vary over time due to process variation, data retention issues, and program disturb conditions. A storage system can calibrate the read threshold voltage using data from a decoded codeword read from a wordline in the memory. For example, the storage system can use the data instead of syndrome weight in a bit error rate estimate scan (BES). As another example, the storage system can use the data to generate a bit error rate distribution, which can be used instead of a cell voltage distribution histogram. Using these techniques can help reduce latency and power consumption, increase throughput, and improve quality of service.