An improved chip interface circuit and chip are disclosed. The circuit includes: a voltage divider circuit, including a first resistor, a second resistor and a switch; an input gate circuit, including a MOS transistor P1 and a MOS transistor N1; one end of the first resistor is connected to the input terminal, and the drains of P1 and N1 are connected to the first terminal, wherein the first terminal is used to connect the main circuit of the chip, and the switch is turned on when the input terminal receives a high-voltage input voltage. The circuit uses low-voltage transistors combined with a voltage divider circuit to realize the chip interface circuit, thereby achieving good interface speed characteristics, and avoiding the problem that the chip cannot work normally when the operating voltage is low due to the high threshold voltage of the high-voltage transistor.

The present disclosure relates to a memory device comprising: an array of memory cells; and an access management architecture providing a secure access to a test mode of the array of memory cells,
the access management architecture comprising: a register group comprising data identifying the memory device; a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness; a non volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature; a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells.
The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device as well as to a method for managing access to a memory array into a test mode.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die having a first bonding surface that is formed with a first set of contacts patterned with a first connection pitch. A second semiconductor die has a second bonding surface that is formed with a second set of contacts patterned with a second connection pitch. The second set of contacts are further patterned with a paired offset. The second semiconductor die is bonded to the first semiconductor die such that the first set of contacts is disposed in opposed electrical engagement with at least a portion of the second set of contacts.

A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation

A system and an operating method thereof include at least a system under test (SUT) having collection of flash storages including hardware of array of flash storages, collection of partitions including logical volumes, a kernel subsystem including operating system, and an application layer including services, applications, systems, or a combination thereof; test drivers configured to drive tests, wherein the tests are configured for testing the SUT, test fixtures configured to generate test data sets corresponding to the test drivers, observers configured to track test results of test cases created in accordance with the test drivers and the test data sets, wherein the test results include metrics, and archives configured to store historical data of the test cases.

A system and an operating method thereof include at least a system under test (SUT) having collection of flash storages including hardware of array of flash storages, collection of partitions including logical volumes, a kernel subsystem including operating system, and an application layer including services, applications, systems, or a combination thereof; test drivers configured to drive tests, wherein the tests are configured for testing the SUT, test fixtures configured to generate test data sets corresponding to the test drivers, observers configured to track test results of test cases created in accordance with the test drivers and the test data sets, wherein the test results include metrics, and archives configured to store historical data of the test cases.

A memory testing circuit and method are disclosed, the redesigning of a memory to be tested through incorporation therein a testing circuit includes a self-test circuit incorporating a decoder circuit, and a VPPIO I/O module incorporating an encoder circuit and having multiple functions including digital I/O, high analog voltage I/O and current I/O. An oscillator module embedded in the multiplexer circuit provides a clock signal for the testing. The VPPIO I/O module is configured to convert, by the self-test circuit, a stimulating input from a single signal pin to a parallel signal recognizable by the memory and an analog voltage/current signal, thereby accomplishing proper testing of the memory. This enables a single signal pin to test all functions of one memory, thereby increasing the number of memory dies on a wafer tested in parallel by a test instrument and reducing the testing time per wafer as well as testing cost.

A memory testing circuit and method are disclosed, the redesigning of a memory to be tested through incorporation therein a testing circuit includes a self-test circuit incorporating a decoder circuit, and a VPPIO I/O module incorporating an encoder circuit and having multiple functions including digital I/O, high analog voltage I/O and current I/O. An oscillator module embedded in the multiplexer circuit provides a clock signal for the testing. The VPPIO I/O module is configured to convert, by the self-test circuit, a stimulating input from a single signal pin to a parallel signal recognizable by the memory and an analog voltage/current signal, thereby accomplishing proper testing of the memory. This enables a single signal pin to test all functions of one memory, thereby increasing the number of memory dies on a wafer tested in parallel by a test instrument and reducing the testing time per wafer as well as testing cost.

A data storage device includes a flash memory and a controller. The controller is coupled to the flash memory and includes a ROM which stores a boot code. In an initialization procedure of the data storage device, the controller does not access the flash memory and receives a debug code from an external device, and executes the boot code and the debug code to complete the initialization procedure.