An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

A resistor-capacitor (RC) sensor circuit of an electronic device is driven to a drive voltage using a representative copy of a current that drives an electronic circuit line of the electronic device. The RC sensor circuit is to sample voltages that are indicative of an RC time constant of the electronic circuit line. A first sample voltage is determined by sampling a first representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current over a first time period. A second sample voltage is determined by sampling a second representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current over a second time period. A ratio of the first sample voltage and the second sample voltage is indicative of the RC time constant of the electronic circuit line.

Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.

A memory device includes a cell array including a memory cell that includes a variable resistance element, a reference resistor configured to provide a resistance varying according to an adjustment code, and a read circuit configured to read data that is stored in the memory cell, based on a resistance of the variable resistance element and the resistance of the reference resistor. The memory device further includes a reference adjustment circuit configured to obtain a first calibration code corresponding to a temperature variation, and a second calibration code corresponding to a process variation, and perform an arithmetic operation on the obtained first calibration code and the obtained second calibration code, to obtain the adjustment code.

A memory system includes: a plurality of nonvolatile memories; a controller connected to the plurality of nonvolatile memories via a plurality of channels that includes a plurality of memory physical layer circuits arranged corresponding to the plurality of channels, respectively, one or more pads for calibration corresponding to the plurality of memory physical layer circuits, and a processor that controls the plurality of memory physical layer circuits. A single reference resistor is connected to the plurality of memory physical layer circuits via the pad. An output based on a ZQ calibration of the plurality of memory physical layer circuits is wired-OR connected to the single reference resistor via the one or more pads. The processor performs a calibration for each of the plurality of memory physical layer circuits in a time division manner using the single reference resistor.

Apparatus and associated methods relate to an I/O bank impedance calibration circuit having (a) a replica master resistor coupled to an external precision resistor, and (b) a control circuit configured to calibrate an output impedance of the master resistor to generate a calibrated code to control a replica slave resistor in each bank. In an illustrative example, a signal applied to the replica master resistor may be compared against a programmable reference signal. The control circuit may generate the calibrated code, in response to the comparison result, to calibrate the output impedance of the replica master resistor. By implementing the replica master resistor and the replica slave resistor, impedances of a large number of IOs or banks may be calibrated by the impedance calibration circuit using a single one reference pin.

A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature. While the NVM array is heated to the target temperature, a current distribution is obtained by measuring a plurality of currents of a subset of NVM cells of the NVM array, each NVM cell of the NVM array is programmed to one of a logically high state or a logically low state, and first and second pass/fail (P/F) tests on each NVM cell of the NVM array are performed. A bit error rate is calculated based on the current distribution and the first and second P/F tests.

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including determining first values of a metric that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory device. The operations further include determining second values of the metric based on the first values, and adjusting valley margins of the memory cell in accordance with the second values of the metric.