Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.

A memory device, and an operating method of the memory device and a host device are provided. The method of operating a memory device includes receiving a command for requesting an Eye Open Monitor (EOM) operation performance from a host device, receiving pattern data including data and non-data from the host device, performing the EOM operation which performs an error count to correspond to the data, and does not perform the error count on the non-data, and transmitting an EOM response signal including the error count result to the host device.

An apparatus with a memory array having a plurality of memory cells. The apparatus also including a memory built-in self-test circuit to test the memory array. The memory built-in self-test circuit includes one or more processing devices to write a data pattern to one or more memory cells to be tested in the memory array, pause for a time period corresponding to a predetermined pause time setting, and read the written data pattern from the one or more memory cells after the time period has elapsed. The predetermined pause time setting is automatically adjusted based on memory device conditions, which can include the temperature of the apparatus.

Automatic memory overclocking, including: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting passing the memory stability test; and generating a profile including the overclocked memory frequency setting.

A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

A semiconductor device includes: a drift detection circuit that retrieves a previously-determined first delay amount of a reference signal passing through a circuit element at a first timing, determines a second delay amount of the reference signal passing through the circuit element at a second timing, and outputs a drift amount that is a difference between the first and second delay amounts; and a delay amount adjustment circuit that retrieves a previously-determined third delay amount of a first signal transmitted to an external device at the first timing, determines a fourth delay amount based on the third delay amount and the drift amount as a delay amount to be applied to the first signal in a period after the second timing, and transmits the first signal to which the fourth delay amount has been applied, to the external device.

Embodiments relate to a test method, a computer apparatus, and a computer-readable storage medium. The test method includes: writing first data into a target memory cell; performing reverse writing on the target memory cell; reading second data stored in the target memory cell after the reverse writing; determining whether the second data are the same as the first data; and determining that write recovery time of the target memory cell fails when the second data are the same as the first data. The present disclosure can make an effective test of determining whether the write recovery time fails.

Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.

A method of testing a memory device includes steps as follows. Commands that meet a specification of the memory device are used. A random decision is performed on the plurality of commands to generate varied patterns, so that a testing device can test the memory device according to the varied patterns, where each of the varied patterns includes a sequence of one or more commands randomly selected from the plurality of commands.

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.