A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.

Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

An memory subsystem of an information handling system includes a memory module and a controller. The memory module includes a Registering Clock Driver (RCD) configured to receive a clock signal. The RCD includes a delay setting and a clock delay circuit to provide a selectable delayed clock signal based upon the delay setting. The memory module further includes a power management integrated circuit (PMIC) with a plurality of switching regulators. The PMIC receives the delayed clock signal and clocks the switching regulators based upon the delayed clock signal. The controller sets the first delay setting.

A memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The memory controller includes a monitor circuit to generate a monitor signal indicating at least one characteristic that varies based on a variation in a manufacturing process condition under which the memory controller was manufactured; a digitization circuit to digitize the monitor signal at a plurality of timings to generate a plurality of digitized monitor signals, each of the plurality of digitized monitor signals having a first size; and a compression circuit to compress the plurality of digitized monitor signals data into first data having the first size.

A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

In an embodiment, a differential strobe input squelch circuit includes a squelch sub-circuit that is configured to perform operations including receiving a true strobe signal, a complement strobe signal, and a strobe difference signal that is representative of a difference between the true strobe signal and the complement strobe signal; determining, based on the true strobe signal and the complement strobe signal, whether the strobe difference signal is defined or undefined; and outputting a modified strobe difference signal that is equal to the strobe difference signal when the squelch sub-circuit determines that the strobe difference signal is defined and that is instead equal to a constant strobe-level voltage when the squelch sub-circuit determines that the strobe difference signal is undefined.

Various implementations described herein refer to an integrated circuit having a first memory structure and a second memory structure. The first memory structure is disposed in a first area of the integrated circuit, and the first memory structure has first memory cells with first transistors. The second memory structure is disposed in a second area of the integrated circuit that is different than the first area, and the second memory structure has second memory cells with second transistors that are separate from the first transistors. The second transistors of the second memory cells are arranged to provide an output oscillating frequency for detecting variation of performance of the first transistors of the first memory cells.

A memory device includes a first data strobe pad; a strobe signal generation circuit suitable for generating a read data strobe signal based on a read timing signal; a monitoring receiver suitable for receiving the read data strobe signal fed back through the first data strobe pad according to a monitoring enable signal; a sampler suitable for generating a sampling clock by sampling the fed back read data strobe signal according to a random clock; a first counter suitable for generating a first counting signal by counting the random clock; a second counter suitable for generating a second counting signal by counting the sampling clock; and a duty detector suitable for generating a duty ratio detection signal based on the first counting signal and the second counting signal.

Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.