Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.

A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.

Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.

A test device capable of measuring characteristics of respective transistors constituting a memory cell is provided. The test device for testing a SRAM connects a resistor to a bit line on one side of a memory cell selected by a word line selection circuit and a bit line selection circuit of the SRAM. In a manner that a selected transistor and a resistor of the memory cell constitute a source follower circuit, the test device applies a voltage to each portion of the memory cell, applies an input voltage to a gate of the transistor constituting the source follower circuit, and inputs an output voltage outputted from a source of the transistor constituting the source follower circuit.

A semiconductor memory device includes: a plurality of banks each suitable for refreshing at least one word line corresponding to a refresh address according to a row active signal; a refresh control circuit suitable for controlling, in response to a refresh command, an activation timing of the row active signal according to mode signals and a counting signal; a refresh counter suitable for generating the counting signal by counting the number of times the row active signal is activated, and generating sequence signals which are sequentially activated; and a detection circuit suitable for generating flag signals by combining the sequence signals, and generating a detection signal according to a corresponding one of the flag signals when any of the mode signals is activated, wherein the refresh counter is initialized by the detection signal.

An information handling system includes a processor that runs a maximum memory stress test of a memory module with a refresh rate of memory devices set to a first refresh rate. Then, the processor may receive a power consumption of the memory module. Also, the processor may receive the temperature of the memory devices, and may set the refresh rate to a second refresh rate. The processor may continuously receive both the power consumption of the memory module and the temperature of the memory devices. Based on the continuously received temperature, the processor may determine whether the temperature of the memory devices exceeds a second threshold temperature. If so, the processor may store a first setting as a refresh setting for the memory module. Otherwise, the processor may store a second setting as the refresh setting for the memory module.

A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

A memory circuit includes: memory cells each including a storage transistor having a first configuration; and a tracking circuit including: a tracking bit line having first and second intermediary nodes; a tracking word line; a first finger circuit (coupled between the first intermediary node and a reference voltage node) including: a first set of first tracking cells, each including a first shadow transistor having the first configuration; and a second finger circuit (coupled between the second intermediary node and the reference voltage node) including: a second set of second tracking cells, each including a second shadow transistor having the first configuration; gate terminals of the first and second shadow transistors being coupled with the tracking word line; and a switch configured to selectively couple the first intermediary node with the second intermediary node and thereby selectively couple the first and second finger circuits in parallel.