In an SRAM circuit mounted in a semiconductor device, power supply voltage reduction circuits generate reduction voltage obtained by reducing an external power supply voltage. A first power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a drive voltage supplied to a word line driver. A second power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a voltage of a power supply line supplying an operating voltage to a memory cell.

A processing device in a memory system determines a first error rate corresponding to a first set of write-to-read delay times at a first end of a range of write-to-read delay times for a memory device and a second error rate corresponding to a second set of write-to-read delay times at a second end of the range of write-to-read delay times, and determines whether a ratio of the first error rate to the second error rate satisfies a threshold criterion. Responsive to the ratio of the first error rate to the second error rate not satisfying the threshold criterion, the processing device adjusts a read voltage level associated with the range of write-to-read delay times

An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.

The present application discloses a data processing method and apparatus. A specific embodiment of the method includes: preprocessing received to-be-processed input data; obtaining a storage address of configuration parameters of the to-be-processed input data based on a result of the preprocessing and a result obtained by linearly fitting an activation function, the configuration parameters being preset according to curve characteristics of the activation function; acquiring the configuration parameters of the to-be-processed input data according to the storage address; and processing the result of the preprocessing of the to-be-processed input data based on the configuration parameters of the to-be-processed input data and a preset circuit structure, to obtain a processing result. This implementation manner implements the processing of the input data to be processed by using the configuration parameter and the preset circuit structure, without the need to use any special circuit for implementing the activation function, thereby simplifying the circuit structure. In addition, this implementation manner can support multiple types of activation functions, thereby improving the flexibility. With such an embodiment, the processing of the input data to be processed can be realized by using the configuration parameters and the preset circuit structure, without the need of using a special circuit to implement the activation function, thereby simplifying the circuit structure, supporting various activation functions, and improving the flexibility.

Embodiments herein describe a memory system that includes a DRAM module with a plurality of individual DRAM chips. In one embodiment, the DRAM chips are per DRAM addressable (PDA) so that each DRAM chip can use a respective reference voltage (VREF) value to decode received data signals (e.g., DQ or CA signals). During runtime, the VREF value can drift away from its optimal value set when the memory system is initialized. To address possible drift in VREF value, the present embodiments perform VREF calibration dynamically. To do so, the memory system monitors a predefined criteria to determine when to perform VREF calibration. To calibrate VREF value, the memory system may write transmit data and then read out the test data to determine the width of a signal eye using different VREF values. The memory system selects the VREF value that results in the widest signal eye.

Control logic in a memory device receives a request to perform a memory access operation on a memory array of the memory device and determines an operating temperature of the memory device. The control logic further modifies a default magnitude of a source voltage signal based on the operating temperature to a form a modified source voltage signal, causes the modified source voltage signal to be applied to the memory array, and performs the memory access operation on the memory array.

Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

Provided are a fuse blowing method and apparatus for a memory, a storage medium, and an electronic device. The method includes: controlling a memory to enter a test mode, and reducing an internal clock frequency of the memory (S210); starting a fuse blowing load mode, and controlling the memory to enter a fuse blowing mode (S220); enabling internal precharge of the memory, and writing a location of a fuse to be blown into a fuse blowing location register (S230); starting a fuse blowing process of the memory, and disabling the internal precharge after preset time (S240); and controlling the memory to exit the fuse blowing mode and the test mode successively (S250).

A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

Systems and methods for selecting an optimal error recovery procedure for correcting a read error in a solid-state drive are provided. A machine learning model is trained to forecast which error recovery procedure of a plurality of error recovery procedures is most likely to achieve a predetermined goal given a state of a solid-state drive. The predetermined goal is based on at least one of a read latency and a failure rate of the solid-state drive. A current state of the solid-state drive is determined. An error recovery procedure is selected from among the plurality of error recovery procedures by inputting the current state of the solid-state drive into the trained machine learning model, thereby triggering the trained machine learning model to output the selected error recovery procedure. The selected error recovery procedure is executed to recover data from the solid-state drive.