According to one embodiment, a magnetic memory device includes a first memory cell and a control circuit. The first memory cell includes a first magnetoresistance effect element and a first switching element coupled in series. The control circuit is configured to repeatedly apply a first voltage to the first memory cell until a first condition is satisfied in a first operation.

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.

A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.

According to an embodiment, a semiconductor device includes a transmission circuit including first and second transistors coupled in series between a first voltage terminal and a second voltage terminal, and a first common node coupled between the first and second transistors and coupled to a through line, the transmission circuit outputting a signal transferred from an internal circuit to the first common node according to an output control signal; a reception circuit including third and fourth transistors coupled in series between the first voltage terminal and the second voltage terminal, and a second common node coupled between the third and fourth transistors and coupled to the internal circuit, the reception circuit transferring a signal transferred through the through line to the internal circuit according to a first input control signal; and a deterioration acceleration circuit for applying stress to the first and third transistors according to a test signal.

A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.

The present disclosure relates to apparatuses and methods for memory management and more particularly to a memory device structured with internal analogic measurement mode features.

The memory is provided with means for detecting a correct generation of voltage and/or current reference values in the memory device including at least a memory array and a memory controller. The method provides for a JTAG interface in the memory controller and an analogic measurement block in said memory device driven by said JTAG interface.

Some embodiments described herein include a method to validate supply chains for electronic devices using side-channel information in a signature analysis. The method includes sending, to a target device, a first signal associated with a set of codes to be executed by the target device, and then receiving first side-channel information associated with the target device in response to the target device executing the set of codes. The method also includes determining second side-channel information associated with a simulated device in response to the set of codes. The method further includes comparing a discriminatory feature of the first side-channel information with a discriminatory feature of the second side-channel information to determine a characteristic of the target device based on a pre-determined characteristic of the simulated device. Finally, the method includes sending, to a user interface, a second signal associated with the characteristic of the target device.

A memory arrangement comprises a non-volatile memory plane (2), a replacement plane (3), an address select block (302), and a counter arrangement (300) having at least one counter (310 to 312). The at least one counter (310 to 312) is configured to be incremented at a write cycle of the memory arrangement (1). The address select block (302) is configured to switch from the non-volatile memory plane (2) to the replacement plane (3), if a counter value of the at least one counter (310 to 312) is higher than a predetermined limit.

The invention relates to a directional magnetic field generator with a magnetic circuit comprising: a first vertical-axis pole end (37) arranged above a horizontal plane; and at least two second pole ends (28A to 28D) symmetrically arranged on said horizontal plane, the generator further comprising coils arranged such that each magnetic circuit portion connecting two pole ends passes inside at least one coil, these coils being suitable for being connected to circuits for circulating currents of adjustable intensity in selected directions therein.

A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.