A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

An apparatus includes an error read flow component resident on a memory sub-system. The error read flow component can cause performance of a plurality of read recovery operations on a group of memory cells that are programmed or read together, or both. The error read flow component can determine whether a particular read recovery operation invoking the group of memory cells was successful. The error read flow component can further cause a counter corresponding to each of the plurality of read recovery operations to be incremented in response to a determination that the particular read recovery operation invoking the group of memory cells was successful.

Disclosed is an operating method of a storage device which includes a plurality of nonvolatile memory chips. The method includes providing, at the storage device, information of a capacity of each of the plurality of nonvolatile memory chips to an external host device, receiving, at the storage device, information of a plurality of groups from the external host device, performing a reset after receiving the information of the plurality of groups, mapping, at the storage device, the plurality of nonvolatile memory chips with the plurality of groups, and configuring the plurality of nonvolatile memory chips so as to correspond to the plurality of groups, after performing the reset.

Adaptive Double Device Data Correction sparing uses memory addresses in increasing order. The last sparing address is stored as a memory address. Each system address for a processor memory transaction is converted to a memory address. The memory address is compared with the last sparing address to determine the Error Code Correction format for the processor memory transaction.

A non-volatile data storage device includes memory cells arranged in a plurality of blocks and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to determine if a given block is a bad m-bit multi-level block. In an m-bit multi-level block, each memory cell is an m-bit multi-level cell (MLC), m being an integer equal to or greater than 2. Upon determining that the given block is a good m-bit multi-level block, the memory controller assigns the given block to be an m-bit multi-level user block. Upon determining that the given block is a bad m-bit multi-level block, the memory controller determines if the given block is a good n-bit block. In an n-bit block, each memory cell is an n-bit cell, n being an integer less than m. Upon determining that the given block is a good n-bit block, the memory controller assigns the given block to be an n-bit user block or an n-bit write-buffer block.

A storage system determines source addresses, and destination addresses in a storage system, for network traffic. The storage system determines a hash algorithm, from a plurality of hash algorithms. The hash algorithm is to be used across the source addresses for load-balancing the network traffic to the destination addresses. The storage system determines that the hash algorithm more closely meets one or more load-balancing criteria than at least one other hash algorithm, of the plurality of hash algorithms. The storage system distributes the network traffic from the source addresses to the destination addresses in the storage system, with load-balancing according to the determined hash algorithm.

The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.

According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Embodiments of the systems and methods disclosed herein includes a NAND flash memory having a boot volume. The boot volume can include a primary boot partition, a secondary boot partition, and a rootdisk partition. The primary boot partition can be configured to receive a kernel component of a file. The secondary boot partition can be configured to receive a copy of the kernel component of the file. The rootdisk partition can be configured to receive a root filesystem of the file.