A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

A system and related method operate solid-states storage memory. The system performs a first tuning process that has a first set of tuning options, on a first portion of solid-states storage memory. The system identifies one or more second portions of solid-states storage memory, within the first portion of solid-states storage memory that fail readability after the first tuning process. The system performs a second tuning process that has a differing second set of tuning options, on each of the one or more second portions of solid-states storage memory.

An apparatus includes an error read flow component resident on a memory sub-system. The error read flow component can cause performance of a plurality of read recovery operations on a group of memory cells that are programmed or read together, or both. The error read flow component can determine whether a particular read recovery operation invoking the group of memory cells was successful. The error read flow component can further cause a counter corresponding to each of the plurality of read recovery operations to be incremented in response to a determination that the particular read recovery operation invoking the group of memory cells was successful.

The present technology relates to a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, which are assigned as a plurality of normal blocks, a plurality of first replacement blocks, a plurality of second replacement blocks, a first CAM block, and a second CAM block, a peripheral circuit configured to perform an erase operation and a program operation on the plurality of memory blocks, and a control logic configured to control the peripheral circuit to perform a growing bad block check operation on a target block during the program operation on a selected target block among the normal memory blocks.

A test system includes a non-volatile memory device that includes a plurality of memory blocks operating in a multi-plane mode, and a test machine that detects a bad block of the non-volatile memory device. The non-volatile memory device generates a ready/busy signal which is based on whether an erase loop for detection of the bad block progresses. When at least one normal block is detected from the plurality of memory blocks included in planes operating in the multi-plane mode, the non-volatile memory device generates the ready/busy signal having a first busy interval. When all the memory blocks included in the planes operating in the multi-plane mode are detected as bad blocks, the non-volatile memory device generates the ready/busy signal having a second busy interval shorter than the first busy interval.

According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

A memory controller includes a first flash translation layer (FTL) generating a physical address corresponding to a first type logical address received from a host on the basis of information about the first memory blocks, a second FTL generating a physical address corresponding to a second type logical address received from the host on the basis of information about the second memory blocks, and a memory control unit controlling the first memory area or the second memory area to perform an operation on the physical address corresponding to the first type logical address or the physical address corresponding to the second type logical address, wherein the first FTL provides the second FTL with block request information for requesting use of the second memory blocks, and generates the physical address corresponding to the first type logical address received from the host on the basis of block allocation information provided by the second FTL.

Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.

A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data.

Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.