A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

A computer platform is disclosed. The computer platform comprises a non-volatile memory to store fuse override data; and a system on chip (SOC), coupled to the non-volatile memory, including a fuse memory to store fuse data and security micro-controller to receive the fuse override data and perform a fuse override to overwrite the fuse data stored in the fuse memory with the fuse override data.

Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.

Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.

Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

An electronic device includes memory banks and repair circuitry configured to remap data from the memory banks to repair memory elements of the memory banks when a failure occurs. The repair circuitry includes a logic gate configured to receive an output from a memory bank of the memory banks, receive a failure signal indicating whether a corresponding memory element has failed, and transmit the output with a value of the output is based at least in part on the failure signal. The repair circuitry also includes error correction circuitry configured to receive the output via the logic gate and a multiplexer configured to receive the output from the memory bank, receive a repair value, and selectively output the output or the repair value from the repair circuitry as an output of the repair circuitry.

A storage device includes a memory, a write circuit, a read circuit, and a debug information register. The memory includes a data area and a redundant area that corresponds to the data area. The write circuit writes first data specified in a write command to the data area, and first information about a transmission source which has transmitted the write command, to the redundant area. The read circuit reads the first data as second data from the data area, and reads the first information as second information from the redundant area, in response to a read command. The debug information register stores the second information read by the read circuit.

A redundancy analysis method of replacing a faulty part of a memory with at least one spare according to the present embodiment includes: acquiring fault information of the memory; and redundancy-allocating the fault with combinations of the spares to correspond to combination codes corresponding to the combinations of the spares, in which, the redundancy-allocating with the combination of the spare areas includes performing parallel processing on each combination of the spares.

A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.

Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.