A semiconductor memory device includes a memory cell array including a first memory cell group, a first parallel bit test circuit configured to output a first fail signal based on each of the plurality of memory cells included in the first memory cell group being defective, and output a first pass signal based on at least one memory cell among the plurality of memory cells included in the first memory cell group being not defective, and a first latch circuit configured to selectively latch an output of the first parallel bit test circuit. The first latch circuit is configured to latch the output of the first parallel bit test circuit in response to the first parallel bit test circuit outputting the first pass signal The plurality of memory cells included in the first memory cell group are respective connected to different word lines, and connected to the same bit line.