Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.

According to one embodiment, there is provided a memory system including a 1.sup.st memory group, a 2.sup.nd memory group, a power supply voltage adjustment circuit, a 1.sup.st line, a 1.sup.st switch, a 2.sup.nd line, a 3.sup.rd line, and a 4.sup.th line. The power supply voltage adjustment circuit includes a 1.sup.st terminal and a 2.sup.nd terminal. The 1.sup.st line electrically connects the 1.sup.st terminal to the 1.sup.st memory group. The 1.sup.st switch includes a 3.sup.rd terminal, a 4.sup.th terminal, and a 5.sup.th terminal. The 1.sup.st switch electrically connects the 3.sup.rd terminal to the 4.sup.th terminal when turned on. The 2.sup.nd line electrically connects the 1.sup.st terminal to the 3.sup.rd terminal. The 3.sup.rd line electrically connects the 4.sup.th terminal to the 2.sup.nd memory group. The 4.sup.th line electrically connects the 2.sup.nd terminal to the 5.sup.th terminal.

In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

A headset includes a camera a 3D stacked memory configured to store image data captured by the camera, and a System-on-Chip (SoC) configured to process the image data stored in the 3D stacked memory. The 3D stacked memory includes a plurality of first drivers/receivers and a plurality of memory banks that are accessible in parallel. Each memory bank is accessible via a corresponding first driver/receiver. The SoC includes a memory controller with a plurality of second drivers/receivers. The plurality of the second drivers/receivers of the SoC are respectively connected to the plurality of the first drivers/receivers of the 3D stacked memory by a plurality of channels. The SoC and the 3D stacked memory are vertically stacked together. The plurality of the memory banks include at least eight memory banks.

A stacked three-dimensional (3D) memory architecture is provided. An example stacked 3D memory architecture is included in a system and/or device, such as augmented reality glasses. Example augmented reality glasses include a camera, a 3D stacked memory, and a System-on-Chip (SoC). The 3D stacked memory is communicatively coupled with the camera and is configured to store image data captured by the camera. The 3D stacked memory includes a plurality of memory banks. The SoC is coupled with the 3D stacked memory. Additionally, the SoC is vertically stacked with the 3D stacked memory via a plurality of die-to-die interconnections between the SoC and the plurality of memory banks, includes a memory controller for accessing one or more memory banks of the plurality of memory banks, and is configured to process the image data stored in the 3D stacked memory.