A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.

Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.

A semiconductor apparatus includes a fuse array, a word line decoder, a bit line decoder, a bank information comparison circuit, and a rupture circuit. The word line decoder is configured to select a word line of the fuse array based on a bank select address signal. The bit line decoder is configured to select a bit line of the fuse array based on a fail row address signal. The bank information comparison circuit and the rupture circuit are configured to rupture a fuse coupled to the word line and the bit line when a fail bank address signal and the bank select address signal correspond to each other.

Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.

A method of repairing a memory device may include collecting fail information on fail cells in a multi-block memory, classifying the fail cells into first and second types, and repairing the fail cells in the multi-block memory using one or more of a global spare memory, a local spare memory, and a common spare memory, based on the fail information.

Embodiments of the present disclosure provide a method and an apparatus of testing a word line. After repair of a memory array is completed, if a target word line in a failure state exists in the memory array, a second numerical value is written into the target word line, and then it is determined, according to a numerical value outputted by each word line in the memory array, whether there are at least two word lines in an on-state in the memory array; if there are at least two word lines in an on-state simultaneously in the memory array, a current value generated by the target word line in an on-to-off process is detected; when the current value generated by the target word line in the on-to-off process is greater than a preset current threshold, it is determined that the target word line has a repair fault.

The present invention provides a data-storage device. The data-storage device includes a flash memory and a controller. The flash memory has a plurality of blocks and each of the blocks has a plurality of pages. The blocks include a plurality of bad blocks that are labeled as damaged. The controller selects one of the bad blocks as a test block, and reads the pages in the test block to determine whether the pages in the test block are damaged. When all the pages in the test block are undamaged, the controller labels the test block as a spare block.

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

A large-scale integrated circuit with built-in self-repair (BISR) circuitry for enabling redundancy repair for embedded memories in each of a plurality of processor cores with embedded built-in self-test (BIST) circuitry. The BISR circuitry receives and decodes BIST data from the embedded memories into fail signature data in a physical-aware form on which repair analysis can be performed. The fail signature data is reformatted into a unified repair format, such that a fuse encoder circuit can be used to encode fuse patterns in that unified repair format for a repair entity for each of the embedded memories. The fuse patterns are reconfigured into the appropriate order for storing in shadow fuse registers associated with the specific embedded memories.