A system-on-chip module for avoiding redundant memory access is provided, comprising at least one microprocessor, a DRAM and a DRAM controller. The DRAM and the microprocessor are integrated and formed in the system-on-chip module commonly. The DRAM controller is electrically connected between the DRAM and the microprocessor, and includes at least one column cache unit such that each microprocessor is able to perform read or write command to the DRAM through its corresponding column cache unit. Compared with the prior arts, the present invention is beneficial to provide better data access quality, efficiency and lower cost and complexity of the system architecture. Thus, the present invention is believed to be applied widely and having greater industrial applicability.

When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.

A memory-testing circuit configured to perform a test of a memory comprising error-correcting code circuitry comprises repair circuitry configured to allocate a spare row or row block in the memory for a defective row or row block in the memory, a defective row or row block being a row or row block in which a memory word has a number of error bits greater than a preset number, wherein the test of the memory comprises: disabling the error-correcting code circuitry, performing a pre-repair operation, the pre-repair operation comprising: determining whether the memory has one or more defective rows or row blocks, and allocating one or more spare rows or row blocks for the one or more defective rows or row blocks if the one or more spare rows or row blocks are available, and performing a post-repair operation on the repaired memory.

Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.

A system-on-chip module for avoiding redundant memory access is provided, comprising at least one microprocessor, a DRAM and a DRAM controller. The DRAM and the microprocessor are integrated and formed in the system-on-chip module commonly. The DRAM controller is electrically connected between the DRAM and the microprocessor, and includes at least one column cache unit such that each microprocessor is able to perform read or write command to the DRAM through its corresponding column cache unit. Compared with the prior arts, the present invention is beneficial to provide better data access quality, efficiency and lower cost and complexity of the system architecture. Thus, the present invention is believed to be applied widely and having greater industrial applicability.

A determination that a programming operation has been performed on a memory cell can be made. An amount of time that has elapsed since the programming operation has been performed on the memory cell can be identified. A determination as to whether the amount of time that has elapsed satisfies a threshold time condition can be made. In response to determining that the amount of time that has elapsed satisfies the threshold time condition an operation can be performed on the memory cell to change or maintain a voltage condition of the memory cell.

The disclosure is directed to a memory storage device and an automatic error repair method thereof. In an aspect, the memory storage device includes a connection interface configured to receive a write command and a word line address associated with the write command, a memory array including a memory bank which contains an error correction code (ECC) detector, a plurality of memory cells controlled by a word line address, and a plurality of redundant memory cells controlled by a redundant word line address, a fuse blowing controller configured to receive the word line address to blow an electrical fuse of the word line address to enable the plurality of redundant memory cells, and a memory control circuit configured to transfer data from the plurality of memory cells through a bit line into the plurality of redundant memory cells in response to the electrical fuse having been blown.

A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.

A system includes a memory device with multiple memory dies and at least a spare memory die. A processing device is coupled to the memory device. The processing device is to track a value of a write counter representing a number of write operations performed at the multiple memory dies. The processing device is to activate the spare memory die in response to detection of a failure of a first memory die of the multiple memory dies. The processing device is to store an offset value of the write counter in response to the detection of the activation of the spare memory die, the offset value representing the value of the write counter upon activation of the first spare memory die.

A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.