A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.

Systems and methods for repairing a memory. A method includes performing a repair analysis of the embedded memories to produce repair information. The method includes storing the repair information in the registers, where the registers are organized into groups having chains of identical length. The method includes performing collision detection between the repair information in each of the groups. The method includes merging the repair information in each of the groups. The method includes repairing the embedded memories using the merged repair information.

Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

A repair device and a semiconductor device are disclosed, which relate to a technology for supporting a plurality of post package repairs (PPRs). The repair device may include a plurality of PPR fuse sets. The repair device may be configured such that if any one of the plurality of PPR fuse sets is selected, the remaining PPR fuse sets may be initialized.

Various implementations described herein are directed to an integrated circuit having core circuitry with an array of bitcells arranged in columns of bitcells that may represent bits. A first column of bitcells may represent a nearest bit of the bits, and a last column of bitcells may represent a farthest bit of the bits. The integrated circuit may include sense amplifier circuitry coupled to the core circuitry to assist with accessing data stored in the array of bitcells. The integrated circuit may include multiplexer circuitry coupled to the sense amplifier circuitry. The integrated circuit may include first bypass circuitry coupled to outputs of the sense amplifier circuitry at the farthest bit. The integrated circuit may include second bypass circuitry coupled to an output of the multiplexer circuitry at the nearest bit.

A system includes a memory device having a plurality of memory dies and at least a first spare memory die and a processing device coupled to the memory device. The processing device is to perform operations including: tracking a value of a write counter representing a number of write operations performed at the plurality of memory dies; activating the first spare memory die in response to detecting a failure of a first memory die of the plurality of memory dies; storing an offset value of the write counter in response to activating the first spare memory die; and commanding the memory device to modify die trim settings of the first spare memory die at predetermined check point values of the write counter that are offset from the offset value.

A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

A semiconductor memory apparatus may include a first memory apparatus and a second memory apparatus, and may perform various operation modes. The first and second memory apparatuses may independently perform a write operation and a read operation in a first operation mode. The first memory apparatus may perform a write operation and a read operation and the second memory apparatus may perform a write operation in a second operation mode. The second memory apparatus may perform a write operation and a read operation in a third operation mode.

A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array.

A semiconductor memory apparatus may include a first memory apparatus and a second memory apparatus, and may perform various operation modes. The first and second memory apparatuses may independently perform a write operation and a read operation in a first operation mode. The first memory apparatus may perform a write operation and a read operation and the second memory apparatus may perform a write operation in a second operation mode. The second memory apparatus may perform a write operation and a read operation in a third operation mode.